AM1707_16 Datasheet, PDF (69/200 Pages) Texas Instruments – AM1707 ARM® Microprocessor

www.ti.com
AM1707
SPRS637E – FEBRUARY 2010 – REVISED JUNE 2014
6.10.6 EMIFA Electrical Data/Timing
The following assume testing over recommended operating conditions.
No.
19 t_su(DV-CLKH)
20 t_h(CLKH-DIV)
Table 6-19. EMIFA SDRAM Interface Timing Requirements
PARAMETER
Input setup time, read data valid on EMA_D[15:0] before EMA_CLK rising
Input hold time, read data valid on EMA_D[15:0] after EMA_CLK rising
MIN MAX UNIT
1.3
ns
1.5
ns
No.
1
2
3
4
5
6
7
t_c(CLK)
t_w(CLK)
t_d(CLKH-CSV)
t_{oh(CLKH-CSIV)}
t_d(CLKH-DQMV)
t_{oh(CLKH-DQMIV)}
t_d(CLKH-AV)
8
t_oh(CLKH-AIV)
9 t_d(CLKH-DV)
10 t_oh(CLKH-DIV)
11 t_d(CLKH-RASV)
12 t_{oh(CLKH-RASIV)}
13 t_d(CLKH-CASV)
14 t_{oh(CLKH-CASIV)}
15 t_d(CLKH-WEV)
16 t_{oh(CLKH-WEIV)}
17 t_{dis(CLKH-DHZ)}
18 t_{ena(CLKH-DLZ)}
Table 6-20. EMIFA SDRAM Interface Switching Characteristics
PARAMETER
Cycle time, EMIF clock EMA_CLK
Pulse width, EMIF clock EMA_CLK high or low
Delay time, EMA_CLK rising to EMA_CS[0] valid
Output hold time, EMA_CLK rising to EMA_CS[0] invalid
Delay time, EMA_CLK rising to EMA_WE_DQM[1:0] valid
Output hold time, EMA_CLK rising to EMA_WE_DQM[1:0] invalid
Delay time, EMA_CLK rising to EMA_A[12:0] and EMA_BA[1:0] valid
Output hold time, EMA_CLK rising to EMA_A[12:0] and EMA_BA[1:0]
invalid
Delay time, EMA_CLK rising to EMA_D[15:0] valid
Output hold time, EMA_CLK rising to EMA_D[15:0] invalid
Delay time, EMA_CLK rising to EMA_RAS valid
Output hold time, EMA_CLK rising to EMA_RAS invalid
Delay time, EMA_CLK rising to EMA_CAS valid
Output hold time, EMA_CLK rising to EMA_CAS invalid
Delay time, EMA_CLK rising to EMA_WE valid
Output hold time, EMA_CLK rising to EMA_WE invalid
Delay time, EMA_CLK rising to EMA_D[15:0] 3-stated
Output hold time, EMA_CLK rising to EMA_D[15:0] driving
MIN MAX UNIT
10
ns
3
ns
7
ns
1
ns
7
ns
1
ns
7
ns
1
ns
7
ns
1
ns
7
ns
1
ns
7
ns
1
ns
7
ns
1
ns
7
ns
1
ns
Table 6-21. EMIFA Asynchronous Memory Timing Requirements⁽¹⁾
No. PARAMETER
MIN NOM MAX UNIT
READS and WRITES
E t_c(CLK)
2 t_{w(EM_WAIT)}
Cycle time, EMIFA module clock
Pulse duration, EM_WAIT assertion and deassertion
READS
10
ns
2E
ns
12 t_{su(EMDV-EMOEH)}
Setup time, EM_D[15:0] valid before EM_OE high
3
ns
13 t_{h(EMOEH-EMDIV)}
Hold time, EM_D[15:0] valid after EM_OE high
0
ns
14 t_{su (EMOEL-EMWAIT)}
Setup Time, EM_WAIT asserted before end of Strobe Phase⁽²⁾
4E+3
ns
WRITES
28 t_{su (EMWEL-EMWAIT)}
Setup Time, EM_WAIT asserted before end of Strobe Phase⁽²⁾
4E+3
ns
(1) E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL output clock divided by 4.5. As an example, when
SYSCLK3 is selected and set to 100MHz, E=10ns.
(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended
wait states. Figure 6-18 and Figure 6-19 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
Copyright © 2010–2014, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
69
Submit Documentation Feedback
Product Folder Links: AM1707