AM1707_16 Datasheet, PDF (64/200 Pages) Texas Instruments – AM1707 ARM® Microprocessor

AM1707
SPRS637E – FEBRUARY 2010 – REVISED JUNE 2014
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6.10 External Memory Interface A (EMIFA)
EMIFA is one of two external memory interfaces supported on the device. It is primarily intended to
support asynchronous memory types, such as NAND and NOR flash and Asynchronous SRAM. However
the EMIFA also provides a secondary interface to SDRAM.
6.10.1 EMIFA Asynchronous Memory Support
EMIFA supports asynchronous:
• SRAM memories
• NAND Flash memories
• NOR Flash memories
The EMIFA data bus width is up to 16-bits on the ZKB package. The device supports up to fifteen address
lines and an external wait/interrupt input. Up to four asynchronous chip selects are supported by EMIFA
(EMA_CS[5:2]) .
All four chip selects are available on the ZKB package.
Each chip select has the following individually programmable attributes:
• Data Bus Width
• Read cycle timings: setup, hold, strobe
• Write cycle timings: setup, hold, strobe
• Bus turn around time
• Extended Wait Option With Programmable Timeout
• Select Strobe Option
• NAND flash controller supports 1-bit and 4-bit ECC calculation on blocks of 512 bytes.
6.10.2 EMIFA Synchronous DRAM Memory Support
The device ZKB package supports 16-bit SDRAM in addition to the asynchronous memories listed in
Section 6.10.1. It has a single SDRAM chip select (EMA_CS[0]). SDRAM configurations that are
supported are:
• One, Two, and Four Bank SDRAM devices
• Devices with Eight, Nine, Ten, and Eleven Column Address
• CAS Latency of two or three clock cycles
• Sixteen Bit Data Bus Width
• 3.3V LVCMOS Interface
Additionally, the SDRAM interface of EMIFA supports placing the SDRAM in Self Refresh and Powerdown
Modes. Self Refresh mode allows the SDRAM to be put into a low power state while still retaining memory
contents. Powerdown mode achieves even lower power, except the processor must periodically wake the
SDRAM up and issue refreshes if data retention is required.
Finally, note that the EMIFA does not support Mobile SDRAM devices. Table 6-17 below shows the
supported SDRAM configurations for EMIFA.
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Peripheral Information and Electrical Specifications
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