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AM1707_16 Datasheet, PDF (1/200 Pages) Texas Instruments – AM1707 ARM® Microprocessor | |||
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AM1707
SPRS637E â FEBRUARY 2010 â REVISED JUNE 2014
AM1707 ARM® Microprocessor
1 AM1707 ARM Microprocessor
1.1 Features
1
⢠375- and 456-MHz ARM926EJ-S⢠RISC Core
â 32-Bit and 16-Bit (Thumb®) Instructions
â Single-Cycle MAC
â ARM Jazelle® Technology
â Embedded ICE-RT⢠for Real-Time Debug
⢠ARM9⢠Memory Architecture
â 16KB of Instruction Cache
â 16KB of Data Cache
â 8KB of RAM (Vector Table)
â 64KB of ROM
⢠Enhanced Direct Memory Access Controller 3
(EDMA3):
â 2 Transfer Controllers
â 32 Independent DMA Channels
â 8 Quick DMA Channels
â Programmable Transfer Burst Size
⢠128KB of RAM Memory
⢠3.3-V LVCMOS I/Os (Except for USB Interfaces)
⢠Two External Memory Interfaces:
â EMIFA
⢠NOR (8- or 16-Bit-Wide Data)
⢠NAND (8- or 16-Bit-Wide Data)
⢠16-Bit SDRAM with 128-MB Address Space
â EMIFB
⢠32-Bit or 16-Bit SDRAM with 256-MB
Address Space
⢠Three Configurable 16550-Type UART Modules:
â UART0 with Modem Control Signals
â 16-Byte FIFO
â 16x or 13x Oversampling Option
â Autoflow Control Signals (CTS, RTS) on UART0
Only
⢠LCD Controller
⢠Two Serial Peripheral Interfaces (SPIs) Each with
One Chip Select
⢠Programmable Real-Time Unit Subsystem
(PRUSS)
â Two Independent Programmable Real-Time Unit
(PRU) Cores
⢠32-Bit Load-Store RISC Architecture
⢠4KB of Instruction RAM per Core
⢠512 Bytes of Data RAM per Core
⢠PRUSS can be Disabled via Software to
Save Power
â Standard Power-Management Mechanism
1
⢠Clock Gating
⢠Entire Subsystem Under a Single PSC Clock
Gating Domain
â Dedicated Interrupt Controller
â Dedicated Switched Central Resource
⢠Multimedia Card (MMC)/Secure Digital (SD) Card
Interface with Secure Data I/O (SDIO)
⢠Two Master and Slave Inter-Integrated Circuit (I2C
Busâ¢)
⢠One Host-Port Interface (HPI) with 16-Bit-Wide
Muxed Address/Data Bus for High Bandwidth
⢠USB 1.1 OHCI (Host) with Integrated PHY (USB1)
⢠USB 2.0 OTG Port with Integrated PHY (USB0)
â USB 2.0 High- and Full-Speed Client
â USB 2.0 High-, Full-, and Low-Speed Host
â End Point 0 (Control)
â End Points 1,2,3,4 (Control, Bulk, Interrupt or
ISOC) RX and TX
⢠Three Multichannel Audio Serial Ports (McASPs):
â Six Clock Zones and 28 Serial Data Pins
â Supports TDM, I2S, and Similar Formats
â DIT-Capable (McASP2)
â FIFO Buffers for Transmit and Receive
⢠10/100 Mbps Ethernet MAC (EMAC):
â IEEE 802.3 Compliant (3.3-V I/O Only)
â RMII Media-Independent Interface
â Management Data I/O (MDIO) Module
⢠Real-Time Clock (RTC) with 32-kHz Oscillator and
Separate Power Rail
⢠One 64-Bit General-Purpose Timer (Configurable
as Two 32-Bit Timers)
⢠One 64-Bit General-Purpose Watchdog Timer
(Configurable as Two 32-Bit General-Purpose
Timers)
⢠Three Enhanced Pulse Width Modulators
(eHRPWMs):
â Dedicated 16-Bit Time-Base Counter with
Period and Frequency Control
â 6 Single Edge, 6 Dual Edge Symmetric, or 3
Dual Edge Asymmetric Outputs
â Dead-Band Generation
â PWM Chopping by High-Frequency Carrier
â Trip Zone Input
⢠Three 32-Bit Enhanced Capture (eCAP) Modules:
â Configurable as 3 Capture Inputs or 3 Auxiliary
Pulse Width Modulator (APWM) Outputs
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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