AM1707_16 Datasheet, PDF (121/200 Pages) Texas Instruments – AM1707 ARM® Microprocessor

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AM1707
SPRS637E – FEBRUARY 2010 – REVISED JUNE 2014
Table 6-66. Additional⁽¹⁾ SPI1 Master Timings, 5-Pin Option^{(2) (3)} (continued)
No.
22 t_{d(SCS_SPC)M}
23 t_{d(ENA_SPC)M}
PARAMETER
Delay from SPI1_SCS active
to first SPI1_CLK^{(7) (8) (9)}
Delay from assertion of
SPI1_ENA low to first
SPI1_CLK edge.⁽¹⁰⁾
Polarity = 0, Phase = 0,
to SPI1_CLK rising
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Polarity = 1, Phase = 0,
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
Polarity = 0, Phase = 0,
to SPI1_CLK rising
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Polarity = 1, Phase = 0,
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
MIN
2P - 5
MAX
UNIT
0.5t_c(SPC)M + 2P - 5
ns
2P - 5
0.5t_c(SPC)M + 2P - 5
3P + 3
0.5t_c(SPC)M + 3P + 3
ns
3P + 3
0.5t_c(SPC)M + 3P + 3
(7) If SPI1_ENA is asserted immediately such that the transmission is not delayed by SPI1_ENA.
(8) In the case where the master SPI is ready with new data before SPI1_SCS assertion.
(9) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(10) If SPI1_ENA was initially deasserted high and SPI1_CLK is delayed.
Table 6-67. Additional⁽¹⁾ SPI1 Slave Timings, 4-Pin Enable Option^{(2) (3)}
No.
PARAMETER
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Delay from final
24
t_{d(SPC_ENAH)S}
SPI1_CLK edge to
slave deasserting
SPI1_ENA.
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
MIN
1.5 P - 3
MAX
UNIT
2.5 P + 19
– 0.5t_c(SPC)M + 1.5 P - 3 – 0.5t_c(SPC)M + 2.5 P + 19
ns
1.5 P - 3
2.5 P + 19
– 0.5t_c(SPC)M + 1.5 P - 3 – 0.5t_c(SPC)M + 2.5 P + 19
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-63).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
Table 6-68. Additional⁽¹⁾ SPI1 Slave Timings, 4-Pin Chip Select Option^{(2) (3)}
No.
25 t_{d(SCSL_SPC)S}
26 t_{d(SPC_SCSH)S}
27 t_{ena(SCSL_SOMI)S}
28 t_{dis(SCSH_SOMI)S}
PARAMETER
Required delay from SPI1_SCS asserted at slave to first
SPI1_CLK edge at slave.
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Required delay from final
SPI1_CLK edge before
SPI1_SCS is deasserted.
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Delay from master asserting SPI1_SCS to slave driving
SPI1_SOMI valid
Delay from master deasserting SPI1_SCS to slave 3-stating
SPI1_SOMI
MIN
2P
0.5t_c(SPC)M + P + 5
P+5
0.5t_c(SPC)M + P + 5
P+5
MAX
UNIT
ns
ns
P + 19 ns
P + 19 ns
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-63).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
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Peripheral Information and Electrical Specifications 121
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