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MSP430FR5972 Datasheet, PDF (68/142 Pages) Texas Instruments – Mixed‑Signal Microcontrollers
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MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
SLASE66A – APRIL 2015 – REVISED MAY 2015
www.ti.com
6.11.8 DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU
intervention. For example, the DMA controller can be used to move data from the ADC12_B conversion
memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA
controller reduces system power consumption by allowing the CPU to remain in sleep mode, without
having to awaken to move data to or from a peripheral.
Table 6-9. DMA Trigger Assignments (1)
TRIGGER
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
CHANNEL 0
DMAREQ
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2 CCR0 CCIFG
TA3 CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
Reserved
Reserved
AES Trigger 0(2)
AES Trigger 1(2)
AES Trigger 2(2)
UCA0RXIFG
UCA0TXIFG
UCA1RXIFG
UCA1TXIFG
UCB0RXIFG (SPI)
UCB0RXIFG0 (I2C)
UCB0TXIFG (SPI)
UCB0TXIFG0 (I2C)
UCB0RXIFG1 (I2C)
UCB0TXIFG1 (I2C)
UCB0RXIFG2 (I2C)
UCB0TXIFG2 (I2C)
UCB1RXIFG (SPI)
UCB1RXIFG0 (I2C)
UCB1TXIFG (SPI)
UCB1TXIFG0 (I2C)
CHANNEL 1
DMAREQ
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2 CCR0 CCIFG
TA3 CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
Reserved
Reserved
AES Trigger 0(2)
AES Trigger 1(2)
AES Trigger 2(2)
UCA0RXIFG
UCA0TXIFG
UCA1RXIFG
UCA1TXIFG
UCB0RXIFG (SPI)
UCB0RXIFG0 (I2C)
UCB0TXIFG (SPI)
UCB0TXIFG0 (I2C)
UCB0RXIFG1 (I2C)
UCB0TXIFG1 (I2C)
UCB0RXIFG2 (I2C)
UCB0TXIFG2 (I2C)
UCB1RXIFG (SPI)
UCB1RXIFG0 (I2C)
UCB1TXIFG (SPI)
UCB1TXIFG0 (I2C)
ADC12 end of conversion(3) ADC12 end of conversion(3)
27
Reserved
28
Reserved
29
MPY ready
30
DMA2IFG
31
DMAE0
Reserved
Reserved
MPY ready
DMA0IFG
DMAE0
(1) If a reserved trigger source is selected, no trigger is generated.
(2) Only on devices with AES. Reserved on devices without AES.
(3) Only on devices with ADC. Reserved on devices without ADC.
CHANNEL 2
DMAREQ
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2 CCR0 CCIFG
TA3 CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
Reserved
Reserved
AES Trigger 0(2)
AES Trigger 1(2)
AES Trigger 2(2)
UCA0RXIFG
UCA0TXIFG
UCA1RXIFG
UCA1TXIFG
UCB0RXIFG (SPI)
UCB0RXIFG0 (I2C)
UCB0TXIFG (SPI)
UCB0TXIFG0 (I2C)
UCB0RXIFG1 (I2C)
UCB0TXIFG1 (I2C)
UCB0RXIFG2 (I2C)
UCB0TXIFG2 (I2C)
UCB1RXIFG (SPI)
UCB1RXIFG0 (I2C)
UCB1TXIFG (SPI)
UCB1TXIFG0 (I2C)
ADC12 end of
conversion (3)
Reserved
Reserved
MPY ready
DMA1IFG
DMAE0
68
Detailed Description
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Product Folder Links: MSP430FR5972 MSP430FR59721 MSP430FR5970 MSP430FR5922 MSP430FR59221
MSP430FR5872 MSP430FR58721 MSP430FR5870
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