MSP430FR5972 Datasheet, PDF (60/142 Pages) Texas Instruments – Mixed‑Signal Microcontrollers

MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
SLASE66A – APRIL 2015 – REVISED MAY 2015
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6.4 Interrupt Vector Table and Signatures
The interrupt vectors, the power-up start address, and signatures are located in the address range
0FFFFh to 0FF80h. Table 6-3 summarizes the content of this address range.
The power-up start address or reset vector is located at 0FFFFh to 0FFFEh. It contains the 16-bit address
pointing to the start address of the application program.
The interrupt vectors start at 0FFFDh extending to lower addresses. Each vector contains the 16-bit
address of the appropriate interrupt-handler instruction sequence.
The vectors programmed into the address range from 0FFFFh to 0FFE0h are used as BSL password (if
enabled by the corresponding signature)
The signatures are located at 0FF80h extending to higher addresses. Signatures are evaluated during
device start-up. Starting from address 0FF88h extending to higher addresses a JTAG password can
programmed. The password can extend into the interrupt vector locations using the interrupt vector
addresses as additional bits for the password.
Refer to the chapter "System Resets, Interrupts, and Operating Modes, System Control Module (SYS)" in
the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx Family User's Guide
(SLAU367) for details.
Table 6-3. Interrupt Sources, Flags, Vectors, and Signatures
INTERRUPT SOURCE
System Reset
Power-Up, Brownout, Supply
Supervisor
External Reset RST
Watchdog Time-out (Watchdog
mode)
WDT, FRCTL MPU, CS, PMM
Password Violation
FRAM uncorrectable bit error
detection
FRAM access time error
MPU segment violation
Software POR, BOR
System NMI
Vacant Memory Access
JTAG Mailbox
FRAM bit error detection
MPU segment violation
User NMI
External NMI
Oscillator Fault
Comparator_E
Timer_B TB0
Timer_B TB0
Watchdog Timer (Interval Timer
Mode)
Reserved
INTERRUPT FLAG
SVSHIFG
PMMRSTIFG
WDTIFG
WDTPW, FRCTLPW, MPUPW, CSPW, PMMPW
UBDIFG
ACCTEIFG
MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG,
MPUSEG3IFG
PMMPORIFG, PMMBORIFG
(SYSRSTIV) ^{(1) (2)}
VMAIFG
JMBNIFG, JMBOUTIFG
CBDIFG, UBDIFG
MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG,
MPUSEG3IFG
(SYSSNIV) ^{(1) (3)}
NMIIFG, OFIFG
(SYSUNIV) ^{(1) (3)}
Comparator_E interrupt flags
(CEIV) ⁽¹⁾
TB0CCR0.CCIFG
TB0CCR1.CCIFG ... TB0CCR6.CCIFG,
TB0CTL.TBIFG
(TB0IV) ⁽¹⁾
WDTIFG
Reserved
SYSTEM
INTERRUPT
Reset
(Non)maskable
(Non)maskable
Maskable
Maskable
Maskable
Maskable
Maskable
WORD
ADDRESS
0FFFEh
0FFFCh
0FFFAh
0FFF8h
0FFF6h
0FFF4h
0FFF2h
0FFF0h
PRIORITY
highest
(1) Multiple source flags
(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space
(3) (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
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Detailed Description
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MSP430FR5872 MSP430FR58721 MSP430FR5870