MSP430FR5972 Datasheet, PDF (21/142 Pages) Texas Instruments – Mixed‑Signal Microcontrollers

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MSP430FR5972, MSP430FR59721, MSP430FR5970, MSP430FR5922, MSP430FR59221
MSP430FR5872, MSP430FR58721, MSP430FR5870
SLASE66A – APRIL 2015 – REVISED MAY 2015
4.4 Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for
example, if the device is in test mode). For details of the settings for each pin and schematics of the
multiplexed ports, see Section 6.11.22.
BUFFER TYPE NOMINAL
(STANDARD) VOLTAGE
LVCMOS
3.0 V
Analog
3.0 V
Power (DVCC)
3.0 V
Power (AVCC)
3.0 V
(1) Only for Input pins.
HYSTERESIS
Y ⁽¹⁾
N
N
N
Table 4-3. Buffer Type
PU OR PD
Programmable
N/A
N/A
N/A
NOMINAL
PU OR PD
STRENGTH
(µA)
See Table 5-11
N/A
N/A
N/A
OUTPUT
DRIVE
STRENGTH
(mA)
OTHER
CHARACTERISTICS
See
Section 5.12.5.1
N/A
See analog modules in
Section 5 for details
N/A
SVS enables hysteresis on
DVCC
N/A
4.5 Connection of Unused Pins
Table 4-4 lists the correct termination of all unused pins.
Table 4-4. Connection of Unused Pins⁽¹⁾
PIN
POTENTIAL
COMMENT
AVCC
AVSS
Px.0 to Px.7
RST/NMI
PJ.0/TDO
PJ.1/TDI
PJ.2/TMS
PJ.3/TCK
DV_CC
DV_SS
Open
DV_CC or V_CC
Open
Switched to port function, output direction (PxDIR.n = 1)
47-kΩ pullup or internal pullup selected with 10-nF (2.2 nF⁽²⁾) pulldown
The JTAG pins are shared with general-purpose I/O function (PJ.x). If these pins are not used, they
should be set to port function and output direction. When used as JTAG pins, these pins should
remain open.
TEST
Open
This pin always has an internal pulldown enabled.
(1) Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.0 to Px.7 unused pin connection
guidelines.
(2) The pulldown capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire JTAG
mode with TI tools like FET interfaces or GANG programmers.
Copyright © 2015, Texas Instruments Incorporated
Terminal Configuration and Functions
21
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