CP3UB26 Datasheet, PDF (67/364 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with USB and CAN Interfaces

CP3UB26
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SNOSAE7E – APRIL 2005 – REVISED JANUARY 2014
11 TRIPLE CLOCK AND RESET
The Triple Clock and Reset module generates a 12 MHz Main Clock and a 32.768 kHz Slow Clock from
external crystal networks or external clock sources. It provides various clock signals for the rest of the
chip. It also provides the main system reset signal, a power-on reset function, Main Clock prescalers to
generate two additional low-speed clocks, and a 32-kHz oscillator start-up delay. Figure 11-1 is a block
diagram of the Triple Clock and Reset module.
Figure 11-1. Triple Clock and Reset Module
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TRIPLE CLOCK AND RESET
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