CP3UB26 Datasheet, PDF (31/364 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with USB and CAN Interfaces

CP3UB26
www.ti.com
SNOSAE7E – APRIL 2005 – REVISED JANUARY 2014
6.4.3 Static Zone 0 Configuration Register (SZCFG0)
The SZCFG0 register is a word-wide, read/write register that controls the timing and bus characteristics of
Zone 0 memory accesses. Zone 0 is used for the on-chip flash memory (including the boot area, program
memory, and data memory).
At reset, the register is initialized to 069Fh. The register format is shown below.
7
BW
15
WAIT
HOLD
RBE
WBR
BW
FRE
IPST
IPRE
6
WBR
5
RBE
4
3
HOLD
2
0
WAIT
Reserved
12
11
10
9
8
FRE
IPRE
IPST
Res.
The Memory Wait field specifies the number of TIW (internal wait state) clock cycles added for each memory access,
ranging from 000b for no additional TIW wait cycles to 111b for seven additional TIW wait cycles. These bits are ignored if
the SZCFG0.FRE bit is set.
The Memory Hold field specifies the number of T_hold clock cycles used for each memory access, ranging from 00b for no
T_hold cycles to 11b for three T_hold clock cycles. These bits are ignored if the SZCFG0.FRE bit is set.
The Read Burst Enable enables burst cycles on 16-bit reads from 8-bit bus width regions of the address space. Because
the flash program memory is required to be 16-bit bus width, the RBE bit is a don’t care bit. This bit is ignored when the
SZCFG0.FRE bit is set.
0 – Burst read disabled.
1 – Burst read enabled.
The Wait on Burst Read bit controls if a wait state is added on burst read transaction. This bit is ignored, when
SZCFG0.FRE bit is set or when SZCFG0.RBE is clear.
0 – No TBW on burst read cycles.
1 – One TBW on burst read cycles.
The Bus Width bit controls the bus width of the zone. The flash program memory must be configured for 16-bit bus width.
0 – 8-bit bus width.
1 – 16-bit bus width (required).
The Fast Read Enable bit controls whether fast read bus cycles are used. A fast read operation takes one clock cycle. A
normal read operation takes at least two clock cycles.
0 – Normal read cycles.
1 – Fast read cycles.
The Post Idle bit controls whether an idle cycle follows the current bus cycle, when the next bus cycle accesses a different
zone. No idle cycles are required for on-chip accesses.
0 – No idle cycle (recommended).
1 – Idle cycle inserted.
The Preliminary Idle bit controls whether an idle cycle is inserted prior to the current bus cycle, when the new bus cycle
accesses a different zone. No idle cycles are required for on-chip accesses.
0 – No idle cycle (recommended).
1 – Idle cycle inserted.
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