CP3UB26 Datasheet, PDF (10/364 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with USB and CAN Interfaces

CP3UB26
SNOSAE7E – APRIL 2005 – REVISED JANUARY 2014
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3.17 TIMING AND WATCHDOG MODULE
The Timing and Watchdog Module (TWM) contains a Real- Time timer and a Watchdog unit. The Real-
Time Clock Timing function can be used to generate periodic real-time based system interrupts. The timer
output is one of 16 inputs to the Multi-Input Wake-Up module which can be used to exit from a power-
saving mode. The Watchdog unit is designed to detect the application program getting stuck in an infinite
loop resulting in loss of program control or “runaway” programs. When the watchdog triggers, it resets the
device. The TWM is clocked by the low-speed System Clock.
3.18 VERSATILE TIMER UNIT
The Versatile Timer Unit (VTU) module contains four independent timer subsystems, each operating in
either dual 8- bit PWM configuration, as a single 16-bit PWM timer, or a 16-bit counter with two input
capture channels. Each of the four timer subsystems offer an 8-bit clock prescaler to accommodate a wide
range of frequencies.
3.19 Triple Clock and Reset
The Triple Clock and Reset module generates a high-speed main System Clock from an external crystal
network. It also provides the main system reset signal and a power-on reset function.
This module generates a slow System Clock (32.768 kHz) from an optional external crystal network. The
Slow Clock is used for operating the device in a low-power mode. The 32.768 kHz external crystal network
is optional, because the low speed System Clock can be derived from the highspeed clock by a prescaler.
Also, two independent clocks divided down from the high speed clock are available on output pins.
The Triple Clock and Reset module provides the clock signals required for the operation of the various
CP3UB26 onchip modules. From external crystal networks, it generates the Main Clock, which can be
scaled up to 24 MHz from an external 12 MHz input clock, and a 32.768 kHz secondary System Clock.
The 12 MHz external clock is primarily used as the reference frequency for the on-chip PLL. The clock for
modules which require a fixed clock rate (e.g. the CVSD/ PCM transcoder) is also generated through
prescalers from the 12 MHz clock. The PLL may be used to drive the highspeed System Clock through a
prescaler. Alternatively, the high speed System Clock can be derived directly from the 12 MHz Main
Clock.
In addition, this module generates the device reset by using reset input signals coming from an external
reset and various on-chip modules.
3.20 Power Management
The Power Management Module (PMM) improves the efficiency of the device by changing the operating
mode and power consumption to match the required level of activity.
The device can operate in any of four power modes:
• Active: The device operates at full speed using the high-frequency clock. All device functions are fully
operational.
• Power Save: The device operates at reduced speed using the Slow Clock. The CPU and some
modules can continue to operate at this low speed.
• Idle: The device is inactive except for the Power Management Module and Timing and Watchdog
Module, which continue to operate using the Slow Clock.
• Halt: The device is inactive but still retains its internal state (RAM and register contents).
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DEVICE OVERVIEW
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