TMS320TCI6614 Datasheet, PDF (65/188 Pages) Texas Instruments – Communications Infrastructure KeyStone SoC

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Table 5-1
AIDx ⁽¹⁾ Bit
TMS320TCI6614
Communications Infrastructure KeyStone SoC
SPRS671—June 2011
Available Memory Page Protection Schemes (Part 2 of 2)
Local Bit Description
1
0
Only accesses by system masters and IDMA are permitted (includes EDMA and IDMA accesses initiated by the DSP).
1
1
End of Table 5-1
All accesses permitted.
1 x = 0, 1, 2, 3, 4, 5
Faults are handled by software in an interrupt (or an exception, programmable within the CorePac interrupt
controller) service routine. A DSP or DMA access to a page without the proper permissions will:
• Block the access — reads return 0, writes are ignored
• Capture the initiator in a status register — ID, address, and access type are stored
• Signal event to DSP interrupt controller
The software is responsible for taking corrective action to respond to the event and resetting the error status in the
memory controller. For more information on memory protection for L1D, L1P, and L2, see the C66x CorePac User
Guide in2.8 ‘‘Related Documentation from Texas Instruments’’ on page 37.
Copyright 2011 Texas Instruments Incorporated
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