TMS320TCI6614 Datasheet, PDF (11/188 Pages) Texas Instruments – Communications Infrastructure KeyStone SoC

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1 TMS320TCI6614 Features
• Four TMS320C66x™ DSP Core Subsystems, Each With
– 1.2 GHz C66x Fixed/Floating-Point DSP Core
› 32 GMacs/Core for Fixed Point @ 1.2 GHz
› 16 GFlops/Core for Floating Point @ 1.2 GHz
– Memory
› 32K Byte L1P Per Core
› 32K Byte L1D Per Core
› 1024K Byte Local L2 Per Core
• ARM Cortex A8 Microprocessor
– ARMv7-Compatible, Dual-Issue, In-Order
Execution Engine
– Includes Neon Media Coprocessor for Advanced
SIMD Media Processing Architecture
– Includes VFP Coprocessor
– Memory
› 500K Byte Local L2
› 256K Byte L2 Cache
› 32K Byte L1I
› 32K Byte L1D
• Multicore Shared Memory Controller (MSMC)
– 2048K Byte MSMC SRAM Memory Shared by Four
DSP Cores
– Memory Protection Unit for Both MSM SRAM and
DDR3_EMIF
• Hardware Coprocessors
– Two Enhanced Coprocessors for Turbo Decoding
› Supports WCDMA/HSPA/HSPA+/TD-SCDMA,
LTE, and WiMAX
› Supports Up To 548 Mbps for LTE and Up to
353 Mbps for WCDMA
› Supports Advanced Receiver Algorithms Such
as IRC, Turbo PIC/SIC, and 2x4/4x4 MIMO
› Low DSP Overhead – HW Interleaver Table
Generation and CRC Check
– Four Viterbi Decoders
› Supports More Than 38 Mbps @ 40 bit Block Size
– Two WCDMA Receive Acceleration Coprocessors
› Up to 256 Users @ 8 Fingers w/o Measurement
– WCDMA Transmit Acceleration Coprocessor
› Up to 256 Users With Two Radio Links and
Diversity
– Two Fast Fourier Transform Coprocessors
› 2048 pt FFT in 4.8 μs
– Bit Rate Coprocessor
› WCDMA/HSPA+, TD-SCDMA, LTE, and WiMAX
Uplink and Downlink Bit Processing
› Includes Encoding, Rate Matching/Dematching,
Segmentation, Multiplexing, and More
› Supports Up To 914 Mbps for LTE and 405 Mbps
for WCDMA/TD-SCDMA
TMS320TCI6614
Communications Infrastructure KeyStone SoC
SPRS671—June 2011
• Multicore Navigator
– 8192 Multipurpose Hardware Queues with Queue
Manager
– Packet-Based DMA for Zero-Overhead Transfers
• Network Coprocessors
– Packet Accelerator Enables Support for
› Transport Plane IPsec, GTP-U, SCTP, PDCP
› L2 User Plane PDCP (RoHC, Air Ciphering)
› 1 Gbps Wire Speed Throughput at 1.5M Packets
Per Second
– Security Accelerator Engine Enables Support for
› IPSec, SRTP, 3GPP and WiMAX Air Interface, and
SSL/TLS Security
› ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC,
CMAC, GMAC, AES, DES, 3DES, Kasumi, SNOW
3G, SHA-1, SHA-2 (256-bit Hash), MD5
› Up to 2.8 Gbps Encryption Speed
• Four Rake/Search Accelerators (RSA) for
– Chip Rate Processing for WCDMA Rel'99, HSDPA,
and HSDPA+
– Reed-Muller Decoding
• Peripherals
– Six Lane SerDes-Based Antenna Interface (AIF2)
› Operating at Up to 6.144 Gbps
› Compliant with CPRI Standards for 3G / 4G
(WCDMA, LTE TDD, LTE FDD, TD-SCDMA, and
WiMAX)
– Four Lanes of SRIO 2.1
› 5 GBaud Operation Per Lane
› Supports Direct I/O, Message Passing
– Two Lanes PCIe Gen2
› Supports Up To 5 GBaud
– Hyperlink
› Supports Connections to Other KeyStone
Architecture Devices Providing Resource
Scalability
› 4 Lanes of Operation
› Supports Combined Rate of Up to 50 Gbaud
– Ethernet MAC Subsystem (EMAC)
› Two SGMII Ports
› IEEE1588 Support
– 64-Bit DDR3 Interface with Speeds up to 1333 MHz
– EMIF16 Interface
– Two UART Interfaces
– I²C Interface
– 32 GPIO pins
– SPI Interface
– USIM Interface
– Semaphore Module
– Twelve 64-Bit Timers
– Three On-Chip PLLs
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phase of development. Characteristic data and other specifications are design
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