TMS320TCI6614 Datasheet, PDF (184/188 Pages) Texas Instruments – Communications Infrastructure KeyStone SoC

TMS320TCI6614
Communications Infrastructure KeyStone SoC
SPRS671—June 2011
www.ti.com
• T=0 and T=1 transmission protocol support
– T = 0 protocol
› Hardware error handling of WWT timer time-out
› Delayed release of I/O data line after successful completion of last byte transmission
– T = 1 protocol
› Transmit protocol (T) of type 1 (TD1 character equal to xH01) (asynchronous half-duplex block
transmission protocol)
› Character waiting time (CWT) management (hardware-timer based)
› Block waiting time (BWT) management (hardware-timer based)
› Block guard time (BGT) management (hardware-timer based)
› Need to keep parity checking at character level without acknowledgement (i.e. no repeat)
• Provide an external clock (FSCK) between 1 MHz and 5 MHz
• ATR procedure
– Hardware identification of character coding convention (direct/inverse) from TS character with update
for processing of subsequent characters (T0, Tai...etc)
– Software processing of PPS/PTS procedure
– Software identification of procedure bytes of PTS0 and PTS1 with update of protocol type T and
transmission factor value Fi/Di T = 1 protocol
– Hardware management of block length (interpretation of LEN character)
– Hardware checking of EDC error code, if LRC is used.
– Hardware error handling of:
› LEN block length error (in Rx mode)
› Character parity check in complement to EDC error.
› CWT, BWT and BGT timers time-out (with IT generation)
Note—Note—If CRC used, EDC error code checking should be done by software. Handling of PCB
erroneous encoding should be done by software.
8.34 EMIF16 Peripheral
The EMIF16 module provides an interface between DSP and external memories such as NAND and NOR flash. For
more information, see the External Memory Interface (EMIF16) for KeyStone Devices User Guide in 2.8 ‘‘Related
Documentation from Texas Instruments’’ on page 37.
8.35 Emulation Features and Capability
8.35.1 Advanced Event Triggering (AET)
The TMS320TCI6614 device supports advanced event triggering (AET). This capability can be used to debug
complex problems as well as understand performance characteristics of user applications. AET provides the
following capabilities:
• Hardware Program Breakpoints: specify addresses or address ranges that can generate events such as halting
the processor or triggering the trace capture.
• Data Watchpoints: specify data variable addresses, address ranges, or data values that can generate events
such as halting the processor or triggering the trace capture.
• Counters: count the occurrence of an event or cycles for performance monitoring.
• State Sequencing: allows combinations of hardware program breakpoints and data watchpoints to precisely
generate events for complex sequences.
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Copyright 2011 Texas Instruments Incorporated