TMS320DM6443_15 Datasheet, PDF (65/219 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6443
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SPRS282G – DECEMBER 2005 – REVISED AUGUST 2010
3.3.3 DSP Boot
For C64x+ booting, the state of the DSP_BT pin is sampled at reset. If DSP_BT is low, the ARM will be
the master of C64x+ and control booting (Host Boot mode). If DSP_BT is high, the C64x+ will boot itself
coming out of device reset (Self-Boot mode). Table 3-7 shows a summary of the DSP boot modes.
DSP_BT
0
DSP
BOOT MODE
Host Boot
ARM
BOOT MODE
Internal Boot
0
Host Boot
External Boot
1
Self Boot
Any, except HPI
1
Host Boot
HPI
Table 3-7. DSP Boot Modes
DSPBOOTADDR
REGISTER VALUE
BRIEF DESCRIPTION
Programmable
ARM sets an internal DSP memory location in DSPBOOTADDR
register where valid DSP code resides and loads code to this
internal DSP memory through DMA prior to releasing DSP reset.
Programmable
ARM sets an external DSP memory location in DSPBOOTADDR
register (EMIFA or DDR2) where valid DSP code resides prior to
releasing DSP reset.
0x4220 0000 Default EMIFA Base Address
Programmable
ARM sets a DSP memory location in the DSPBOOTADDR
register. HPI loads code into the DM6443 memory map with the
entry point set to the memory location specified in the
DSPBOOTADDR register. Once the HPI completes loading the
code, the ARM should release the DSP from reset.
3.3.3.1 Host-Boot Mode
In host boot mode, the ARM is the master and controls the reset and boot of the C64x+. The C64x+ DSP
remains powered-off after device reset. The ARM is responsible for enabling power to the C64x+ and
releasing it from reset (PSC MMR bits: MDCTL[39].LRST and MRSTOUT1.MRSTz[39]). Prior to releasing
the C64x+ reset, the ARM must program the address from which the C64x+ will begin execution in the
DSPBOOTADDR register.
3.3.3.2 Self-Boot Mode
In self-boot mode, the C64x+ power domain is turned on and the C64x+ DSP is released from reset
without ARM intervention. The C64x+ begins execution from the default EMIFA address (0x4220 0000)
contained within the DSPBOOTADDR register. The C64x+ begins execution with instruction (L1P) cache
enabled.
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