TMS320DM6443_15 Datasheet, PDF (189/219 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6443
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6.17.2.2 SPI Master Mode Timings (Clock Phase = 1)
SPRS282G – DECEMBER 2005 – REVISED AUGUST 2010
Table 6-74. Timing Requirements for SPI Master Mode [Clock Phase = 1]⁽¹⁾ (see Figure 6-60)
NO.
13
t_su(DIV-CLKL)
Setup time, SPI_DI (input) valid before SPI_CLK
(output) rising edge
14
t_su(DIV-CLKH)
Setup time, SPI_DI (in put) valid before SPI_CLK
(output) falling edge
15 t_h(CLKL-DIV)
Hold time, SPI_DI (input) valid after SPI_CLK
(output) rising edge
16
t_h(CLKH-DIV)
Hold time, SPI_DI (input) valid after SPI_CLK
(output) falling edge
Clock Polarity = 0
Clock Polarity = 1
Clock Polarity = 0
Clock Polarity = 1
-594
MIN
0.5P + 9.4
UNIT
MAX
ns
0.5P + 9.4
ns
0.5P - 4.5
ns
0.5P - 4.5
ns
(1) P = Period of the SPI module clock in nanoseconds (SYSCLK5).
Table 6-75. Switching Characteristics Over Recommended Operating Conditions for SPI Master Mode
[Clock Phase = 1] (see Figure 6-60)
NO.
PARAMETER
17 t_d(CLKL-DOV)
18 t_d(CLKH-DOV)
19 t_{d(ENL-CLKH/L)}
20 t_{d(CLKH/L-ENH)}
Delay time, SPI_CLK (output) falling edge to SPI_DO
(output) transition
Clock Polarity = 0
Delay time, SPI_CLK (output) rising edge to SPI_DO
(output) transition
Clock Polarity = 1
Delay time, SPI_EN[1:0] (output) falling edge to first SPI_CLK (output) rising or
falling edge^{(1) (2) (3)}
Delay time, SPI_CLK (output) rising or falling edge to SPI_EN[1:0] (output)
rising edge^{(1) (2)}
-594
MIN
-4
-4
2P + 0.5C - 2.3
1P - 0.2
UNIT
MAX
5 ns
5 ns
ns
ns
(1) P = Period of the SPI module clock in nanoseconds (SYSCLK5).
(2) This delay can be increased under software control by the C2TDELAY register bit field in the SPIDELAY register.
(3) C = Period of SPI_CLK signal in ns.
20
SPI_EN
SPI_CLK
(Clock Polarity = 0)
SPI_CLK
(Clock Polarity = 1)
SPI_DI
(Input)
19
15
13
MSB IN
16
14
DATA
LSB IN
SPI_DO
(Output)
MSB OUT
17
DATA
18
LSB OUT
Figure 6-60. SPI Master Mode External Timing (Clock Phase = 1)
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Peripheral and Electrical Specifications 189
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