TMS320DM6443_15 Datasheet, PDF (169/219 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6443
www.ti.com
SPRS282G – DECEMBER 2005 – REVISED AUGUST 2010
Table 6-55. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and
Data Output With Respect to VCLK^{(1) (2)} (see Figure 6-49)
NO.
PARAMETER
17 t_c(VCLK)
18 t_w(VCLKH)
Cycle time, VCLK
Pulse duration, VCLK high (positive-edge clocking)
Pulse duration, VCLK high (negative-edge clocking)
19 t_w(VCLKL)
Pulse duration, VCLK low (positive-edge clocking)
Pulse duration, VCLK low (negative-edge clocking)
20 t_t(VCLK)
Transition time, VCLK
21 t_{d(VCLKINH-VCLKH)} Delay time, VCLKIN high to VCLK high
22 t_{d(VCLKINL-VCLKL)} Delay time, VCLKIN low to VCLK low
23 t_{d(VCLK-VCTLV)}
Delay time, VCLK negative edge to VCTL valid
Delay time, VCLK positive edge to VCTL valid
Delay time, VCLK negative edge to VCTL invalid
24 t_{d(VCLKL-VCTLIV) Delay time, VCLK positive edge to VCTL invalid}
Delay time, VCLK negative edge to VDATA valid
25 t_{d(VCLK-VDATAV) Delay time, VCLK positive edge to VDATA valid}
Delay time, VCLK negative edge to VDATA invalid
26 t_{d(VCLKL-VDATAIV)}
Delay time, VCLK positive edge to VDATA invalid
MODE ⁽³⁾
RGB
YCC
RGB
YCC
-594
MIN
MAX
13.33
160
H - 1.3⁽⁴⁾ H - 0.3⁽⁴⁾
L - 1.3⁽⁴⁾ L - 0.3⁽⁴⁾
L + 0.3⁽⁴⁾ L + 1.3⁽⁴⁾
H + 0.3⁽⁴⁾ H + 1.3⁽⁴⁾
3
2
12
2
12
7.5
6.9
2
1.5
6.8
6.3
2.1
2.5
1.9
2.1
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1) The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the
rising edge of VCLK is referenced. When in negative edge clocking mode, the falling edge of VCLK is referenced.
(2) VCLKIN = VPBECLK
(3) RGB and YCC modes utilize different data pins. RGB mode uses data pins: R[7:0], G[7:0], and B[7:0]. YCC mode uses data pins:
COUT[7:0] and YOUT[7:0].
(4) H and L are the high and low pulse widths of the input clock to the VPBE, respectively. For example, if VPBECLK is used as the input
clock and it has a high pulse duration of 6.67 ns, the resulting high pulse duration of VCLK, if positive-edge clocking is selected, will be a
MAX of 6.37 ns and a MIN of 5.27 ns.
VCLKIN^(A)
21
22
VCLK
(Positive Edge
Clocking)
VCLK
(Negative Edge
Clocking)
VCTL^(B)
VDATA^(C)
17
23
25
18
19
24
20
20
26
A. VCLKIN = VPBECLK
B. VCTL = HSYNC, VSYNC, LCD_FIELD, and LCD_OE
C. VDATA = COUT[7:0], YOUT[7:0], R[7:0], G[7:0], and B[7:0]
Figure 6-49. VPBE Control and Data Output Timing With Respect to VCLK
Copyright © 2005–2010, Texas Instruments Incorporated
Peripheral and Electrical Specifications 169
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