TMS320DM6443_15 Datasheet, PDF (117/219 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6443
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SPRS282G – DECEMBER 2005 – REVISED AUGUST 2010
6.7.3 ARM/DSP Communications Interrupts
The INTGEN register is used for generating interrupts between the ARM and DSP. The INTGEN register
format is shown in Figure 6-18. Table 6-24 describes the register bit fields. The ARM may generate an
interrupt to the DSP by setting one of the four INTDSP[3:0] bits or the INTNMI bit. The interrupt bit
automatically self clears and the corresponding DSP[3:0]STAT or NMISTAT bit is automatically set to
indicate that the interrupt was generated. After servicing the interrupt, the DSP clears the status bit by
writing ‘0’. The ARM may poll the status bit to determine when the DSP has completed servicing the
interrupt. The DSP may generate an interrupt to the ARM in the same manner using the INTARM[1:0] bits
and monitor ARM interrupt servicing via the ARM[1:0]STAT bits.
Figure 6-18. INTGEN Register
31
30
29
28
27
Reserved
ARM1 ARM0
STAT STAT
R-00
R/W-0 R/W-0
Reserved
R-0000
15
14
13
12
11
Reserved
INT INT
ARM1 ARM0
Reserved
R-00
R/W-0 R/W-0
R-0000
LEGEND: R = Read, W = Write, n = value at reset
24
23
22
21
20
DSP3 DSP2 DSP1 DSP0
STAT STAT STAT STAT
R/W-0 R/W-0 R/W-0 R/W-0
8
7
6
5
4
INT INT INT INT
DSP3 DSP2 DSP1 DSP0
R/W-0 R/W-0 R/W-0 R/W-0
19
17
Reserved
R-000
3
1
Reserved
R-000
16
NMI
STAT
R/W-0
0
INT
NMI
R/W-0
Table 6-24. INTGEN Register Bit Fields Descriptions
Name
ARM1STAT
ARM0STAT
DSP3STAT
DSP2STAT
DSP1STAT
DSP0STAT
NMISTAT
INTARM1
INTARM0
INTDSP3
INTDSP2
INTDSP1
INTDSP0
INTNMI
DSP to ARM Int1 Status/Clear⁽¹⁾
DSP to ARM Int0 Status/Clear⁽¹⁾
ARM to DSP Int3 Status/Clear⁽¹⁾
ARM to DSP Int2 Status/Clear⁽¹⁾
ARM to DSP Int1 Status/Clear⁽¹⁾
ARM to DSP Int0 Status/Clear⁽¹⁾
DSP NMI Status/Clear⁽¹⁾
DSP to ARM Int1 Set⁽²⁾
DSP to ARM Int0 Set⁽²⁾
ARM to DSP Int3 Set⁽²⁾
ARM to DSP Int2 Set⁽²⁾
ARM to DSP Int1 Set⁽²⁾
ARM to DSP Int0 Set⁽²⁾
DSP NMI Set⁽²⁾
Description
(1) Write '0' to clear. Writing '1' has no effect.
(2) Write '1' to generate the interrupt. The register bit automatically clears to a value of '0'. Writing a '0' has no effect.
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Peripheral and Electrical Specifications 117
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