TMS320DM6443_15 Datasheet, PDF (202/219 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6443
SPRS282G – DECEMBER 2005 – REVISED AUGUST 2010
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Table 6-88. Timing Requirements for EMAC MII Receive 10/100 Mbit/s⁽¹⁾ (see Figure 6-66)
NO.
1 t_{su(MRXD-MRCLKH)}
Setup time, receive selected signals valid before MRCLK high
2 t_{h(MRCLKH-MRXD)}
Hold time, receive selected signals valid after MRCLK high
(1) Receive selected signals include: MRXD3-MRXD0, MRXDV, and MRXER.
-594
MIN MAX
8
8
UNIT
ns
ns
1
2
MRCLK (Input)
MRXD3−MRXD0,
MRXDV, MRXER (Inputs)
Figure 6-66. EMAC Receive Interface Timing
Table 6-89. Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit
10/100 Mbit/s⁽¹⁾ (see Figure 6-67)
NO.
1 t_{d(MTCLKH-MTXD)}
Delay time, MTCLK high to transmit selected signals valid
(1) Transmit selected signals include: MTXD3-MTXD0, and MTXEN.
-594
MIN MAX
5
25
UNIT
ns
1
MTCLK (Input)
MTXD3−MTXD0,
MTXEN (Outputs)
Figure 6-67. EMAC Transmit Interface Timing
202 Peripheral and Electrical Specifications
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