TMS320DM6443_15 Datasheet, PDF (141/219 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6443
www.ti.com
SPRS282G – DECEMBER 2005 – REVISED AUGUST 2010
6.10.2.1 DDR2 Memory Controller Electrical Data/Timing
The Implementing DDR2 PCB Layout on the TMS320DM644x DSP application report (literature number
SPRAAC5) specifies a complete DDR2 interface solution for the DM6443 as well as a list of compatible
DDR2 devices. TI has performed the simulation and system characterization to ensure all DDR2 interface
timings in this solution are met.
TI only supports board designs that follow the guidelines outlined in the Implementing DDR2 PCB Layout
on the TMS320DM644x DSP application report (literature number SPRAAC5).
Table 6-37. Switching Characteristics Over Recommended Operating Conditions for DDR2 Memory
Controller^{(1) (2)}(see Figure 6-25)
NO.
PARAMETER
-594
MIN MAX
1
t_{c(DDR_CLK0)}
Cycle time, DDR_CLK0 for normal DDR2 speed (166 MHz)
6
8
(1) DDR_CLK0 cycle time = 2 x PLL2 - SYSCLK2 cycle time.
(2) The PLL2 Controller must be programmed such that the resulting DDR_CLK0 clock frequency is within the specified range.
UNIT
ns
1
DDR_CLK0
Figure 6-25. DDR2 Memory Controller Clock Timing
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Peripheral and Electrical Specifications 141
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