ADS58J64 Datasheet, PDF (65/81 Pages) Texas Instruments – Quad-Channel, 14-Bit, 1-GSPS Telecom Receiver Device

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7.6.1.1.6.2 Register 08h (address = 08h) [reset = 0h], ADCXX Page
ADS58J64
SBAS807 – JANUARY 2017
Figure 130. Register 8h
7
6
5
4
3
2
1
0
FAST_OVR_THRESHOLD_LOW
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 63. Register 08h Field Descriptions
Bit Field
Type
7-0 FAST_OVR_THRESHOLD_LOW R/W
Reset
0h
Description
These bits set the lower thresholds for the fast OVR. These bits
set the value for the combination of stage 1 and stage 2 and not
sign adjusted.
7.6.1.1.6.3 Register D5h (address = D5h) [reset = 0h], ADCXX Page
Figure 131. Register D5h
7
6
5
0
0
0
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
4
0
R/W-0h
3
CAL_EN
R/W-0h
2
0
R/W-0h
1
0
R/W-0h
0
0
R/W-0h
Bit Field
7-4 0
3
CAL_EN
2-0 0
Table 64. Register D5h Field Descriptions
Type
R/W
R/W
Reset
0h
0h
R/W
0h
Description
Must read or write 0
This bit is the enable calibration bit. This bit must be toggled
during the startup sequence.
0 : Disables calibration
1 : Enables calibration
Must read or write 0
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