ADS58J64 Datasheet, PDF (1/81 Pages) Texas Instruments – Quad-Channel, 14-Bit, 1-GSPS Telecom Receiver Device

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ADS58J64
SBAS807 – JANUARY 2017
ADS58J64 Quad-Channel, 14-Bit, 1-GSPS Telecom Receiver Device
1 Features
•1 Quad Channel
• 14-Bit Resolution
• Maximum Sample Rate: 1 GSPS
• Maximum Output Bandwidth: 250 MHz
• Analog Input Buffer With High-Impedance Input
• Output Options:
– Rx: Decimate-by-2 and -4 Options With
Low-Pass Filter
– 200-MHz Complex Bandwidth or 100-MHz
Real Bandwidth Support
– DPD FB: 2x Decimation With 14-Bit Burst
Mode Output
• 1.1-V_PP Differential Full-Scale Input
• JESD204B Interface:
– Subclass 1 Support
– 1 Lane per ADC Up to 10 Gbps
– Dedicated SYNC Pin for Pair of Channels
• Support for Multi-Chip Synchronization
• 72-Pin VQFN Package (10 mm × 10 mm)
• Power Dissipation: 625 mW/Ch
• Spectral Performance
(Burst Mode, High Resolution):
– f_IN = 190 MHz IF at –1 dBFS:
– SNR: 69 dBFS
– NSD: –153 dBFS/Hz
– SFDR: 86 dBc (HD2, HD3),
95 dBFS (Non HD2, HD3)
– f_IN = 370 MHz IF at –3 dBFS:
– SNR: 68.5 dBFS
– NSD: –152.5 dBFS/Hz
– SFDR: 80 dBc (HD2, HD3),
86 dBFS (Non HD2, HD3)
2 Applications
• Multi-Carrier GSM Cellular Infrastructure
Base Stations
• Multi-Carrier Multi-Mode Cellular Infrastructure
Base Stations
• Telecommunications Receivers
• Telecom DPD Observation Receivers
3 Description
The ADS58J64 is a low-power, wide-bandwidth, 14-
bit, 1-GSPS, quad-channel, telecom receiver device.
The ADS58J64 supports a JESD204B serial interface
with data rates up to 10 Gbps with one lane per
channel. The buffered analog input provides uniform
input impedance across a wide frequency range and
minimizes sample-and-hold glitch energy. The
ADS58J64 provides excellent spurious-free dynamic
range (SFDR) over a large input frequency range with
very low power consumption. The digital signal
processing block includes complex mixers followed
by low-pass filters with decimate-by-2 and -4 options
supporting up to a 200-MHz receive bandwidth. The
ADS58J64 also supports a 14-bit, 500-MSPS output
in burst mode, making the device suitable for a digital
pre-distortion (DPD) observation receiver.
The JESD204B interface reduces the number of
interface lines, thus allowing high system integration
density. An internal phase-locked loop (PLL)
multiplies the incoming analog-to-digital converter
(ADC) sampling clock to derive the bit clock that is
used to serialize the 14-bit data from each channel.
Device Information⁽¹⁾
PART NUMBER PACKAGE
BODY SIZE (NOM)
ADS58J64
VQFN (72)
10.00 mm × 10.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
INAP, INAM
INBP, INBM
SYSREFP,
SYSREFM
CLKINP,
CLKINM
INCP, INCM
INDP, INDM
Simplified Block Diagram
1144b-Bitit
AADDCC
1144b-Bitit
AADDCC
2x
Decimation
High Pass,
Low Pass
2x
Decimation
High Pass,
Low Pass
N
N^NC^CO^O
Burst Mode
JESD204B
CLK
÷ by
PLL
2, 4
x10/x20
1144b-Bitit
AADDCC
1144b-Bitit
AADDCC
2x
Decimation
High Pass,
Low Pass
2x
Decimation
High Pass,
Low Pass
Burst Mode
N
NCO
Configuration
Registers
JESD204B
DAP, DAM
DBP, DBM
TRIGAB
TRIGCD
TRD YAB
TRD YCD
SYNCbAB
SYNCbCD
DCP, DCM
DDP, DDM
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.