ADS58J64 Datasheet, PDF (36/81 Pages) Texas Instruments – Quad-Channel, 14-Bit, 1-GSPS Telecom Receiver Device

ADS58J64
SBAS807 – JANUARY 2017
www.ti.com
7.5.4.3 Eye Diagram
Figure 68 to Figure 71 show the serial output eye diagrams of the ADS58J64 at 7.5 Gbps and 10 Gbps with
default and increased output voltage swing against the JESD204B mask.
Figure 68. Eye at 10-Gbps Bit Rate with
Default Output Swing
Figure 69. Eye at 7.5-Gbps Bit Rate with
Default Output Swing
Figure 70. Eye at 10-Gbps Bit Rate with
Increased Output Swing
Figure 71. Eye at 7.5-Gbps Bit Rate with
Increased Output Swing
7.5.5 Device Configuration
The ADS58J64 can be configured using a serial programming interface, as described in the Register Maps
section. In addition, the device has one dedicated parallel pin (PDN) for controlling the power-down modes. The
ADS58J64 supports a 24-bit (16-bit address, 8-bit data) SPI operation and uses paging to access all register bits.
7.5.5.1 Details of the Serial Interface
The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock), SDIN (serial data input data), and SDOUT (serial data output)
pins. Serially shifting bits into the device is enabled when SEN is low. SDIN serial data are latched at every
SCLK rising edge when SEN is active (low). Data can be loaded in multiples of 24-bit words within a single active
SEN pulse. The first 16 bits form the register address and the remaining eight bits are the register data. The
interface can work with SCLK frequencies from 10 MHz down to very low speeds (of a few hertz) and also with a
non-50% SCLK duty cycle.
7.5.5.1.1 Register Initialization
After power-up, the internal registers must be initialized to the default values. This initialization can be
accomplished in one hardware reset by applying a high pulse on the RESET pin.
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