LM3S812_16 Datasheet, PDF (60/590 Pages) Texas Instruments – Stellaris LM3S812 Microcontroller

The Cortex-M3 Processor
Register 20: Base Priority Mask Register (BASEPRI)
The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is
set to a nonzero value, it prevents the activation of all exceptions with the same or lower priority
level as the BASEPRI value. Exceptions should be disabled when they might impact the timing of
critical tasks. This register is only accessible in privileged mode. For more information on exception
priority levels, see “Exception Types” on page 71.
Base Priority Mask Register (BASEPRI)
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
BASEPRI
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:8
7:5
Name
reserved
BASEPRI
Type
RO
R/W
Reset Description
0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0
Base Priority
Any exception that has a programmable priority level with the same or
lower priority as the value of this field is masked. The PRIMASK register
can be used to mask all exceptions with programmable priority levels.
Higher priority exceptions have lower priority levels.
Value Description
0x0 All exceptions are unmasked.
0x1 All exceptions with priority level 1-7 are masked.
0x2 All exceptions with priority level 2-7 are masked.
0x3 All exceptions with priority level 3-7 are masked.
0x4 All exceptions with priority level 4-7 are masked.
0x5 All exceptions with priority level 5-7 are masked.
0x6 All exceptions with priority level 6-7 are masked.
0x7 All exceptions with priority level 7 are masked.
4:0
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
60
July 14, 2014
Texas Instruments-Production Data