LM3S812_16 Datasheet, PDF (171/590 Pages) Texas Instruments – Stellaris LM3S812 Microcontroller

Stellaris^® LM3S812 Microcontroller
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058
On a read, this register gives the current masked status value of the corresponding interrupt. All of
the bits are R/W1C and this action also clears the corresponding raw interrupt bit in the RIS register
(see page 169).
Masked Interrupt Status and Clear (MISC)
Base 0x400F.E000
Offset 0x058
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PLLLMIS CLMIS IOFMIS MOFMIS LDOMIS BORMIS reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:7
6
5
4
3
2
1
0
Name
reserved
PLLLMIS
CLMIS
IOFMIS
MOFMIS
LDOMIS
BORMIS
reserved
Type
RO
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
RO
Reset
0
0
0
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PLL Lock Masked Interrupt Status
This bit is set when the PLL T_READY timer asserts. The interrupt is cleared
by writing a 1 to this bit.
Current Limit Masked Interrupt Status
This bit is set if the LDO’s CLE output asserts. The interrupt is cleared
by writing a 1 to this bit.
Internal Oscillator Fault Masked Interrupt Status
This bit is set if an internal oscillator fault is detected. The interrupt is
cleared by writing a 1 to this bit.
Main Oscillator Fault Masked Interrupt Status
This bit is set if a main oscillator fault is detected. The interrupt is cleared
by writing a 1 to this bit.
LDO Power Unregulated Masked Interrupt Status
This bit is set if LDO power is unregulated. The interrupt is cleared by
writing a 1 to this bit.
BOR Masked Interrupt Status
This bit is the masked interrupt status for any brown-out conditions. If
set, a brown-out condition was detected. An interrupt is reported if the
BORIM bit in the IMC register is set and the BORIOR bit in the PBORCTL
register is cleared. The interrupt is cleared by writing a 1 to this bit.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
July 14, 2014
171
Texas Instruments-Production Data