LM3S812_16 Datasheet, PDF (234/590 Pages) Texas Instruments – Stellaris LM3S812 Microcontroller

General-Purpose Input/Outputs (GPIOs)
Table 7-3. GPIO Signals (48QFP) (continued)
Pin Name
Pin Number Pin Type Buffer Type^a Description
PE1
36
I/O
TTL
GPIO port E bit 1.
PE2
4
I/O
TTL
GPIO port E bit 2.
PE3
3
I/O
TTL
GPIO port E bit 3.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
7.3 Functional Description
Important: All GPIO pins are inputs by default (GPIODIR=0 and GPIOAFSEL=0), with the exception
of the five JTAG pins (PB7 and PC[3:0]). The JTAG pins default to their JTAG
functionality (GPIOAFSEL=1). A Power-On-Reset (POR) or asserting an external reset
(RST) puts both groups of pins back to their default state.
While debugging systems where PB7 is being used as a GPIO, care must be taken to
ensure that a Low value is not applied to the pin when the part is reset. Because PB7
reverts to the TRST function after reset, a Low value on the pin causes the JTAG
controller to be reset, resulting in a loss of JTAG communication.
Each GPIO port is a separate hardware instantiation of the same physical block (see Figure
7-2 on page 235). The LM3S812 microcontroller contains five ports and thus five of these physical
GPIO blocks.
234
July 14, 2014
Texas Instruments-Production Data