TCA9543A_15 Datasheet, PDF (6/32 Pages) Texas Instruments – TCA9543A Low Voltage 2-Channel I2C Bus Switch With Interrupt Logic And Reset

TCA9543A
SCPS206A – MARCH 2014 – REVISED FEBRUARY 2015
www.ti.com
Electrical Characteristics⁽¹⁾ (continued)
over recommended operating free-air temperature range (unless otherwise noted)
C_i
C_io(OFF) ⁽⁵⁾
PARAMETER
A1, A0
INT1–INT0
RESET
SCL, SDA
SC1–SC0, SD1–SD0
TEST CONDITIONS
V_I = V_CC or GND⁽³⁾
V_I = V_CC or GND⁽³⁾
V_I = V_CC or GND⁽³⁾
V_I = V_CC or GND⁽³⁾, Switch OFF
V_CC
1.65 V to 5.5 V
1.65 V to 5.5 V
1.65 V to 5.5 V
1.65 V to 5.5 V
V_O = 0.4 V, I_O = 15 mA
R_ON
Switch on-state resistance
V_O = 0.4 V, I_O = 10 mA
4.5 V to 5.5 V
3 V to 3.6 V
2.3 V to 2.7 V
1.65 V to 1.95 V
(5) C_io(ON) depends on the device capacitance and load that is downstream from the device.
MIN TYP⁽²⁾
4.5
4.5
4.5
15
6
4
10
5
13
7
16
10
25
MAX
6
6
5.5
19
8
16
20
45
70
UNIT
pF
pF
Ω
7.6 I²C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5)
f_scl
I²C clock frequency
t_sch
I²C clock high time
t_scl
I²C clock low time
t_sp
I²C spike time
t_sds
I²C serial-data setup time
t_sdh
I²C serial-data hold time
t_icr
I²C input rise time
t_icf
I²C input fall time
t_ocf
I²C output fall time
10-pF to 400-pF bus
t_buf
I²C bus free time between stop and start
t_sts
I²C start or repeated start condition setup
t_sth
I²C start or repeated start condition hold
t_sps
I²C stop condition setup
t_vdL(Data) Valid-data time (high to low)⁽³⁾
SCL low to SDA output low valid
t_vdH(Data) Valid-data time (low to high)⁽³⁾
SCL low to SDA output high valid
t_vd(ack)
Valid-data time of ACK condition
ACK signal from SCL low
to SDA output low
C_b
I²C bus capacitive load
STANDARD MODE
I²C BUS
MIN
MAX
0
100
4
4.7
50
250
0 ⁽¹⁾
1000
300
300
4.7
4.7
4
4
1
0.6
FAST MODE
I²C BUS
UNIT
MIN MAX
0
400 kHz
0.6
μs
1.3
μs
50 ns
100
0 ⁽¹⁾
20 + 0.1C_b(2)
20 + 0.1C_b(2)
20 + 0.1C_b(2)
1.3
ns
μs
300 ns
300 ns
300 ns
μs
0.6
μs
0.6
μs
0.6
μs
1 μs
0.6 μs
1
1 μs
400
400 pF
(1) A device internally must provide a hold time of at least 300-ns for the SDA signal (referred to as the V_IH min of the SCL signal), in order
to bridge the undefined region of the falling edge of SCL.
(2) C_b = total bus capacitance of one bus line in pF
(3) Data taken using a 1-kΩ pullup resistor and 50-pF load (see Figure 5)
6
Submit Documentation Feedback
Product Folder Links: TCA9543A
Copyright © 2014–2015, Texas Instruments Incorporated