TCA9543A_15 Datasheet, PDF (22/32 Pages) Texas Instruments – TCA9543A Low Voltage 2-Channel I2C Bus Switch With Interrupt Logic And Reset

TCA9543A
SCPS206A – MARCH 2014 – REVISED FEBRUARY 2015
12 Layout
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12.1 Layout Guidelines
For PCB layout of the TCA9543A, common PCB layout practices should be followed but additional concerns
related to high-speed data transfer such as matched impedances and differential pairs are not a concern for I²C
signal speeds. It is common to have a dedicated ground plane on an inner layer of the board and terminals that
are connected to ground should have a low-impedance path to the ground plane in the form of wide polygon
pours and multiple vias. By-pass and de-coupling capacitors are commonly used to control the voltage on the
VCC terminal, using a larger capacitor to provide additional power in the event of a short power supply glitch and
a smaller capacitor to filter out high-frequency ripple.
In an application where voltage translation is not required, all V_DPUX voltages and V_CC could be at the same
potential and a single copper plane can connect all of the pull-up resistors to the appropriate reference voltage.
In an application where voltage translation is required, V_DPUM, V_DPU0, and V_DPU1, may all be on the same layer of
the board with split planes to isolate different voltage potentials.
To reduce the total I²C bus capacitance added by PCB parasitics, data lines (SCn, SDn and INTn) should be a
short as possible and the widths of the traces should also be minimized (e.g. 5-10 mils depending on copper
weight).
12.2 Layout Example
LEGEND
Partial Power Plane
VIA to Power Plane
Polygonal
Copper Pour
VIA to GND Plane (Inner Layer)
To I2C Master
By-pass/De-coupling
capacitors
V_DPUM
V_DPU0
GND
A0
A1
RESET
INT0
SD0
SC0
GND
GND
V_CC
VCC
SDA
SCL
INT
SC1
SD1
INT1
V_DPU1
Figure 23. Layout Example
22
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