TCA9543A_15 Datasheet, PDF (13/32 Pages) Texas Instruments – TCA9543A Low Voltage 2-Channel I2C Bus Switch With Interrupt Logic And Reset

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TCA9543A
SCPS206A – MARCH 2014 – REVISED FEBRUARY 2015
Programming (continued)
A device generating a message is a transmitter; a device receiving a message is the receiver. The device that
controls the message is the master and the devices that are controlled by the master are the slaves (see
Figure 10).
SDA
SCL
Master
Transmitter/
Receiver
Slave
Receiver
Slave
Transmitter/
Receiver
Master
Transmitter
Master
Transmitter/
Receiver
I²C-Bus
Multiplexer
Slave
Figure 10. System Configuration
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not
limited. Each byte of eight bits is followed by one acknowledge (ACK) bit. The transmitter must release the SDA
line before the receiver can send an ACK bit.
When a slave receiver is addressed, it must generate an ACK after the reception of each byte. Also, a master
must generate an ACK after the reception of each byte that has been clocked out of the slave transmitter. The
device that acknowledges must pull down the SDA line during the ACK clock pulse, so that the SDA line is stable
low during the high pulse of the ACK-related clock period (see Figure 11). Setup and hold times must be taken
into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.
In this event, the transmitter must release the data line to enable the master to generate a stop condition.
Data Output
by Transmitter
Data Output
by Receiver
NACK
SCL From
Master
S
Start
Condition
1
2
8
Figure 11. Acknowledgment on I²C Bus
ACK
9
Clock Pulse for
Acknowledgment
Data is transmitted to the TCA9543A control register using the write mode shown in Figure 12.
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