TCA9543A_15 Datasheet, PDF (15/32 Pages) Texas Instruments – TCA9543A Low Voltage 2-Channel I2C Bus Switch With Interrupt Logic And Reset

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Register Maps (continued)
TCA9543A
SCPS206A – MARCH 2014 – REVISED FEBRUARY 2015
Interrupt Bits
(Read Only)
Channel Selection Bits
(Read/Write)
76 5 43 2 10
X X INT1 INT0 X X B1 B0
Channel 0
Channel 1
INT0
INT1
Figure 15. Control Register
9.6.3 Control Register Definition
One or both SCn/SDn downstream pairs, or channels, are selected by the contents of the control register (see
Table 1). After the TCA9543A has been addressed, the control register is written. The two LSBs of the control
byte are used to determine which channel or channels are to be selected. When a channel is selected, the
channel becomes active after a stop condition has been placed on the I²C bus. This ensures that all SCn/SDn
lines are in a high state when the channel is made active, so that no false conditions are generated at the time of
connection. A stop condition must occur always right after the acknowledge cycle.
Table 1. Control Register Write (Channel Selection), Control Register Read (Channel Status)⁽¹⁾
D7
D6
INT1
INT0
D3
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
D2
B1
B0
COMMAND
0
X
X
1
Channel 0 disabled
Channel 0 enabled
0
X
X
1
Channel 1 disabled
Channel 1 enabled
0
0
0
No channel selected; power-up/reset default state
(1) Channel 0 and channel 1 can be enabled at the same time. Care should be taken not to exceed the maximum bus capacitance.
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