NS16C552 Datasheet, PDF (6/24 Pages) Texas Instruments – PC16552D Dual Universal Asynchronous Receiver/Transmitter with FIFOs†

3 0 AC Electrical Characteristics T_A e 0 C to a70 C V_DD e a5V g10% (Continued)
Symbol
Parameter
Conditions
Min
Max
Units
TRANSMITTER
t_HR
Delay from WR (WR THR)
to Reset Interrupt
40
ns
t_IR
Delay from RD (RD IIR) to Reset
Interrupt (THRE)
40
ns
t_IRS
Delay from Initial INTR Reset
to Transmit Start
8
24
BAUDOUT
Cycles
t_SI
Delay from Initial Write to Interrupt
(Note 1)
16
24
BAUDOUT
Cycles
t_STI
Delay from Start to Interrupt (THRE)
(Note 1)
8
BAUDOUT
Cycles
t_SXA
Delay from Start to TXRDY Active
8
BAUDOUT
Cycles
t_WXI
Delay from Write to TXRDY Inactive
MODEM CONTROL
25
ns
t_MDO
Delay from WR (WR MCR)
to Output
40
ns
t_RIM
Delay to Reset Interrupt from
RD (RD MSR)
78
ns
t_SIM
Delay to Set Interrupt from MODEM Input
40
ns
Note 1 This delay will be lengthened by 1 character time minus the last stop bit time if the transmitter interrupt delay circuit is active (See FIFO Interrupt Mode
Operation)
4 0 Timing Waveforms All timings are referenced to valid 0 and valid 1
External Clock Input (24 MHz Max)
AC Test Points
TL C 9426 – 2
Note 2 The 2 4V and 0 4V levels are the voltages that the inputs are driven to during AC testing
Note 3 The 2 0V and 0 8V levels are the voltages at which the timing tests are made
BAUDOUT Timing
TL C 9426 – 3
TL C 9426 – 4
5