NS16C552 Datasheet, PDF (18/24 Pages) Texas Instruments – PC16552D Dual Universal Asynchronous Receiver/Transmitter with FIFOs†

8 0 Registers (Continued)
Bit 4 This bit is the Break Interrupt (BI) indicator Bit 4 is set
to a logic 1 whenever the received data input is held in the
Spacing (logic 0) state for longer than a full word transmis-
sion time (that is the total time of Start bit a data bits a
Parity a Stop bits) The BI indicator is reset whenever the
CPU reads the contents of the Line Status Register or when
the next valid character is loaded into the Receiver Buffer
Register In the FIFO Mode this condition is associated with
the particular character in the FIFO it applies to It is re-
vealed to the CPU when its associated character is at the
top of the FIFO When break occurs only one zero character
is loaded into the FIFO The next character transfer is en-
abled after SIN goes to the marking state and receives the
next valid start bit
Note Bits 1 through 4 are the error conditions that produce a Receiver Line
Status interrupt whenever any of the corresponding conditions are
detected and the interrupt is enabled
Bit 5 This bit is the Transmitter Holding Register Empty
(THRE) indicator In the 16450 mode bit 5 indicates that the
associated serial channel is ready to accept a new charac-
ter for transmission In addition this bit causes the DUART
to issue an interrupt to the CPU when the Transmit Holding
Register Empty Interrupt enable is set high The THRE bit is
set to a logic 1 when a character is transferred from the
Transmitter Holding Register into the Transmitter Shift Reg-
ister The bit is reset to logic 0 concurrently with the loading
of the Transmitter Holding Register by the CPU In the FIFO
mode this bit is set when the XMIT FIFO is empty it is
cleared when at least 1 byte is written to the XMIT FIFO
Bit 6 This bit is the Transmitter Empty (TEMT) indicator Bit
6 is set to a logic 1 whenever the Transmitter Holding Regis-
ter (THR) and the Transmitter Shift Register (TSR) are both
empty It is reset to a logic 0 whenever either the THR or
TSR contains a data character In the FIFO mode this bit is
set to one whenever the transmitter FIFO and shift register
are both empty
Bit 7 In the 16450 Mode this is a 0 In the FIFO Mode LSR7
is set when there is at least one parity error framing error or
break indication in the FIFO LSR7 is cleared when the CPU
reads the LSR if there are no subsequent errors in the
FIFO
Note The Line Status Register is intended for read operations only Writing
to this register is not recommended as this operation is only used for
factory testing In the FIFO mode the user must load a data byte into
the Rx FIFO in order to write to LSR2–4 LSR0 and LSR7 cannot be
written to in the FIFO mode
8 5 FIFO CONTROL REGISTER
This is a write only register at the same location as the IIR
(the IIR is a read only register) This register is used to en-
able the FIFOs clear the FIFOs set the RCVR FIFO trigger
level and select the type of DMA signalling
Bit 0 Writing a 1 to FCR0 enables both the XMIT and RCVR
FIFOs Resetting FCR0 will clear all bytes in both FIFOs
When changing from FIFO Mode to 16450 Mode and vice
versa data is automatically cleared from the FIFOs This bit
must be a 1 when other FCR bits are written to or they will
not be programmed
Bit 1 Writing a 1 to FCR1 clears all bytes in the RCVR FIFO
and resets its counter logic to 0 The shift register is not
cleared The 1 that is written to this bit position is self-clear-
ing
Bit 2 Writing a 1 to FCR2 clears all bytes in the XMIT FIFO
and resets its counter logic to 0 The shift register is not
cleared The 1 that is written to this bit position is self-clear-
ing
Bit 3 Writing a 1 to FCR3 causes RXRDY and TXRDY oper-
ations to change from mode 0 to mode 1 if FCR0e1
RXRDY Mode 0 When in the 16450 Mode (FCR0 e 0) or
in the FIFO Mode (FCR0 e 1 FCR3 e 0) and there is at
least 1 character in the RCVR FIFO or RCVR Buffer Regis-
ter the RXRDY pin will go low active Once active the
RXRDY pin will go inactive when there are no more charac-
ters in the FIFO or Buffer Register
Baud Rate
50
75
110
134 5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
128000
TABLE IV Baud Rates Divisors and Crystals
1 8432 MHz Crystal
Decimal Divisor
for 16 c Clock
Percent Error
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2
0 026
0 058
0 69
2 86
3 072 MHz Crystal
Decimal Divisor
for 16 c Clock
Percent Error
3840
2560
1745
1428
1280
640
320
160
107
96
80
53
40
27
20
10
5
0 026
0 034
0 312
0 628
1 23
18 432 MHz Crystal
Decimal Divisor
for 16 c Clock
Percent Error
23040
15360
10473
8565
7680
3840
1920
920
640
576
480
320
240
160
120
60
30
21
2 04
9
Note For baud rates of 250k 300k 375k 500k 750k and 1 5M using a 24 MHz crystal causes minimal error
17