NS16C552 Datasheet, PDF (5/24 Pages) Texas Instruments – PC16552D Dual Universal Asynchronous Receiver/Transmitter with FIFOs†

3 0 AC Electrical Characteristics T_A e 0 C to a70 C V_DD e a5V g10%
Symbol
Parameter
Conditions
Min
Max
Units
t_AR
RD Delay from Address
15
ns
t_AW
WR Delay from Address
15
ns
t_DH
Data Hold Time
5
ns
t_DS
Data Setup Time
15
ns
t_HZ
RD to Floating Data Delay
(Note 2)
10
20
ns
t_MR
Master Reset Pulse Width
500
ns
t_RA
Address Hold Time from RD
0
ns
t_RC
Read Cycle Update
29
ns
t_RD
RD Strobe Width
40
ns
t_RVD
Delay from RD to Data
25
ns
t_WA
Address Hold Time from WR
0
ns
t_WC
Write Cycle Update
29
ns
t_WR
WR Strobe Width
40
ns
t_XH
Duration of Clock High Pulse
External Clock (24 MHz Max)
17
ns
t_XL
Duration of Clock Low Pulse
External Clock (24 MHz Max)
17
ns
RC
Read Cycle e t_AR a t_RD a t_RC
84
ns
WC
Write Cycle e t_AW a t_WR a t_WC
84
ns
BAUD GENERATOR
N
Baud Divisor
1
2¹⁶ b 1
t_BHD
t_BLD
RECEIVER
Baud Output Positive Edge Delay
Baud Output Negative Edge Delay
f_X e 24 MHz d2
f_X e 24 MHz d2
45
ns
45
ns
t_RAI
Delay from Active Edge of RD to
Reset Interrupt
78
ns
t_RINT
Delay from Inactive Edge of RD
(RD LSR)
to Reset Interrupt
40
ns
t_RXI
t_SCD
t_SINT
Delay from READ to RXRDY Inactive
Delay from RCLK to Sample Time
Delay from Stop to Set Interrupt
(Note 1)
55
ns
33
ns
2
BAUDOUT
Cycles
Note 1 In the FIFO mode (FCR0 e 1) the trigger level interrupts the receiver data available indication the active RXRDY indication and the overrun error
indication will be delayed 3 RCLKs Status indicators (PE FE BI) will be delayed 3 RCLKs after the first byte has been received For subsequently received bytes
these indicators will be updated immediately after RDRBR goes inactive Timeout interrupt is delayed 8 RCLKs
Note 2 Charge and discharge time is determined by V_OL V_OH and the external loading
Note 3 All AC timings can be met with current loads that don’t exceed 3 2 mA or b80 mA at 100 pF capacitive loading
Note 4 For capacitive loads that exceed 100 pF the following typical derating factors should be used
100 pF k C_L s 150 pF t e (0 1 ns pF)(C_L b 100 pF)
150 pF k C_L s 200 pF t e (0 08 ns pF)(C_L b 100 pF)
I_SINK
t e (0 5 ns mA)(I_SINK mA)
I_SOURCE
t e (0 5 ns mA)(I_SOURCE mA)
Limits I_SOURCE is negative I_SINK s 4 8 mA I_SOURCE s b120 mA C_L s 250 pF
AC Testing Load Circuit
TL C 9426 – 22
4