NS16C552 Datasheet, PDF(19/24 Page) Texas Instruments – PC16552D Dual Universal Asynchronous Receiver/Transmitter with FIFOs†

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

NS16C552 Datasheet, PDF (19/24 Pages) Texas Instruments – PC16552D Dual Universal Asynchronous Receiver/Transmitter with FIFOs†

◁

8 0 Registers (Continued)

RXRDY Mode 1 In the FIFO Mode (FCR0 e 1) when the

FCR3 e 1 and the trigger level or the timeout has been

reached the RXRDY pin will go low active Once it is acti-

vated it will go inactive when there are no more characters

in the FIFO

TXRDY Mode 0 In the 16450 Mode (FCR0 e 0) or in the

FIFO Mode (FCR0 e 1 FCR3 e 0) when there are no

characters in the XMIT FIFO or XMIT Holding Register the

TXRDY pin will go low active Once active the TXRDY pin

will go inactive after the first character is loaded into the

XMIT FIFO or Holding Register

TXRDY Mode 1 In the FIFO Mode (FCR0 e 1 FCR3 e 1)

and when there are no characters in the XMIT FIFO the

TXRDY pin will go low active This pin will become inactive

when the XMIT FIFO is completely full

Bit 4 5 FCR4 to FCR5 are reserved for future use

Bit 6 7 FCR6 and FCR7 are used to designate the interrupt

trigger level When the number of bytes in the RCVR FIFO

equals the designated interrupt trigger level a Received

Data Available Interrupt is activated This interrupt must be

enabled by setting IER0

FCR Bits

RCVR FIFO

Trigger Level (Bytes)

8 6 INTERRUPT IDENTIFICATION REGISTER

In order to provide minimum software overhead during data

character transfers each serial channel of the DUART prior-

itizes interrupts into four levels and records these in the

Interrupt Identification Register The four levels of interrupt

conditions in order of priority are Receiver Line Status Re-

ceived Data Ready Transmitter Holding Register Empty

and MODEM Status

When the CPU reads the IIR the associated DUART serial

channel freezes all interrupts and indicates the highest pri-

ority pending interrupt to the CPU While this CPU access is

occurring the associated DUART serial channel records

new interrupts but does not change its current indication

until the access is complete Table II shows the contents of

the IIR Details on each bit follow

Bit 0 This bit can be used in a prioritized interrupt environ-

ment to indicate whether an interrupt is pending When bit 0

is a logic 0 an interrupt is pending and the IIR contents may

be used as a pointer to the appropriate interrupt service

routine When bit 0 is a logic 1 no interrupt is pending

Bits 1 and 2 These two bits of the IIR identify the highest

priority interrupt pending from those shown in Table V

Bit 3 In the 16450 Mode this bit is 0 In the FIFO Mode this

bit is set along with bit 2 when a timeout interrupt is pending

Bits 4 and 5 These two bits of the IIR are always logic 0

Bits 6 and 7 These two bits are set when FCR0 e 1

(FIFO Mode enabled )

TABLE V Interrupt Control Functions

FIFO

Mode

Only

Interrupt

Identification

Interrupt Set and Reset Functions

Bit 3 Bit 2 Bit 1 Bit 0 Priority

Level

Interrupt Type

Interrupt Source

Interrupt Reset Control

0 001

None

0 1 1 0 Highest Receiver Line Status Overrun Error or Parity Error or

Reading the Line Status

Framing Error or Break Interrupt

0 1 0 0 Second Received Data Available Receiver Data Available or Trigger Reading the Receiver Buffer

Level Reached

below the Trigger Level

1 1 0 0 Second Character Timeout

Indication

No Characters Have Been

Removed from or Input to the

RCVR FIFO During the Last 4 Char

Times and There is at Least 1 Char

in it During This Time

Reading the Receiver

Buffer Register

0 0 1 0 Third Transmitter Holding

Transmitter Holding

Reading the IIR Register (if

Source of Interrupt) or Writing

into the Transmitter Holding

0 0 0 0 Fourth MODEM Status

Clear to Send or Data Set Ready or Reading the MODEM

Ring Indicator or Data Carrier

Detect

Status Register

▷