DS90UB903QSQ Datasheet, PDF (6/45 Pages) Texas Instruments – DS90UB903Q/DS90UB904Q 10 - 43MHz 18 Bit Color FPD-Link III Serializer and Deserializer

DS90UB903Q, DS90UB904Q
SNLS332E – JUNE 2010 – REVISED APRIL 2013
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DS90UB904Q DESERIALIZER PIN DESCRIPTIONS (continued)
Pin Name
PDB
Pin No.
35
LOCK
34
RES
38, 39, 43, 46
BIST MODE
BISTEN
44
PASS
37
FPD-LINK III INTERFACE
RIN+
41
RIN-
42
CMLOUTP
38
CMLOUTN
39
POWER AND GROUND
VDDSSCG
3
VDDIO1/2/3
VDDD
VDDR
VDDCML
VDDPLL
29, 20, 7
17
36
40
45
VSS
DAP
I/O, Type
Description
Input, LVCMOS
w/ pull down
Power down Mode Input Pin.
PDB = H, Deserializer is enabled and is ON.
PDB = L, Deserializer is in Power Down mode. When the Deserializer is in Power
Down. Programmed control register data are NOT retained and reset to default
values.
Output,
LVCMOS
LOCK Status Output Pin.
LOCK = H, PLL is Locked, outputs are active
LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by
OSS_SEL control register. May be used as Link Status.
Reserved.
Pins 38, 39: Route to test point or leave open if unused. See also FPD-LINK III
-
INTERFACE pin description section.
Pin 46: This pin MUST be tied LOW.
Pin 43: Leave pin open.
Input, LVCMOS
w/ pull down
BIST Enable Pin.
BISTEN = H, BIST Mode is enabled.
BISTEN = L, BIST Mode is disabled.
Output,
LVCOMS
PASS Output Pin for BIST mode.
PASS = H, ERROR FREE Transmission
PASS = L, one or more errors were detected in the received payload.
Leave Open if unused. Route to test point (pad) recommended.
Input/Output,
CML
Input/Output,
CML
Output, CML
Output, CML
Non-inverting differential input, bidirectional control channel output. The interconnect
must be AC Coupled with a 100 nF capacitor.
Inverting differential input, bidirectional control channel output. The interconnect must
be AC Coupled with a 100 nF capacitor.
Non-inverting CML Output
Monitor point for equalized differential signal. Test port is enabled via control
registers.
Inverting CML Output
Monitor point for equalized differential signal. Test port is enabled via control
registers.
Power, Digital
Power, Digital
Power, Digital
Power, Analog
Power, Analog
Power, Analog
Ground, DAP
SSCG Power, 1.8V ±5%
Power supply must be connected regardless if SSCG function is in operation.
LVCMOS I/O Buffer Power, The single-ended outputs and control input are powered
from V_DDIO. V_DDIO can be connected to a 1.8V ±5% or 3.3V ±10%
Digital Core Power, 1.8V ±5%
Rx Analog Power, 1.8V ±5%
Bidirectional Channel Driver Power, 1.8V ±5%
PLL Power, 1.8V ±5%
DAP must be grounded. DAP is the large metal contact at the bottom side, located at
the center of the WQFN package. Connected to the ground plane (GND) with at least
16 vias.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6
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