DS90UB903QSQ Datasheet, PDF (5/45 Pages) Texas Instruments – DS90UB903Q/DS90UB904Q 10 - 43MHz 18 Bit Color FPD-Link III Serializer and Deserializer

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DS90UB904Q Pin Diagram
DS90UB903Q, DS90UB904Q
SNLS332E – JUNE 2010 – REVISED APRIL 2013
PASS 37
RES/CMLOUTP 38
RES/CMLOUTN 39
V_DDCML 40
RIN+ 41
RIN- 42
RES 43
BISTEN 44
V_DDPLL 45
RES 46
MODE 47
ID[x] 48
DAP = GND
DS90UB904Q
Deserializer
48-Pin WQFN
(Top View)
24 ROUT[4]
23 ROUT[5]
22 ROUT[6]
21 ROUT[7]
20 V_DDIO2
19 ROUT[8]
18 ROUT[9]
17 V_DDD
16 ROUT[10]
15 ROUT[11]
14 ROUT[12]
13 ROUT[13]
Deserializer - DS90UB904Q
48 Pin WQFN (Top View)
See Package Number RHS0048A
DS90UB904Q DESERIALIZER PIN DESCRIPTIONS
Pin Name
Pin No.
I/O, Type
Description
LVCMOS PARALLEL INTERFACE
ROUT[20:0]
5, 6, 8, 9, 10,
11, 12, 13, 14,
15, 16, 18, 19,
21, 22, 23, 24,
25, 26, 27, 28
Outputs,
LVCMOS
Parallel data outputs.
PCLK
4
Output,
LVCMOS
Pixel Clock Output Pin.
Strobe edge set by RRFB control register.
GENERAL PURPOSE INPUT (GPI)
GPI[3:0]
30, 31, 32, 33
Input, LVCMOS
General-purpose input pins can be used to control and respond to various
commands.
BIDIRECTIONAL CONTROL BUS - I²C COMPATIBLE
SCL
SDA
MODE
2
Input/Output, Clock line for the bidirectional control bus communication
Open Drain SCL requires an external pull-up resistor to V_DDIO.
1
Input/Output, Data line for bidirectional control bus communication
Open Drain SDA requires an external pull-up resistor to V_DDIO.
I²C Mode select
MODE = L, Master mode; Device generates and drives the SCL clock line, where
47
Input, LVCMOS required such as Read. Device is connected to slave peripheral on the bus.
w/ pull up MODE = H, Slave mode (default); Device accepts SCL clock input and attached to an
I²C controller master on the bus. Slave mode does not generate the SCL clock, but
uses the clock generated by the Master for the data transfers.
ID[x]
48
Input, analog
Device ID Address Select
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 4.
CONTROL AND CONFIGURATION
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