DS90UB903QSQ Datasheet, PDF (30/45 Pages) Texas Instruments – DS90UB903Q/DS90UB904Q 10 - 43MHz 18 Bit Color FPD-Link III Serializer and Deserializer

DS90UB903Q, DS90UB904Q
SNLS332E – JUNE 2010 – REVISED APRIL 2013
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The Deserializer GPI[1:0] set to 00 will bypass the on-chip oscillator and an external oscillator to Serializer PCLK
input is required. This allows the user to operate BIST under different frequencies other than the predefined
ranges.
Step 2: Enable AT SPEED BIST by placing the Serializer into BIST mode.
Deserializer will communicate through the bidirectional control channel to configure Serializer into BIST mode.
Once the BIST mode is set, the Serializer will initiate BIST transmission to the Deserializer.
Wait 10 ms for Deserializer to acquire lock and then monitor the LOCK pin transition from LOW to HIGH. At this
point, AT SPEED BIST is operational and the BIST process has begun. The Serializer will start transfer of an
internally generated PRBS data pattern through the high speed serial link. This pattern traverses across the
interconnecting link to the Deserializer. Check the status of the PASS pin; a HIGH indicates a pass, a LOW
indicates a fail. A fail will stay LOW for ½ a clock cycle. If two or more bits in the serial frame fail, the PASS pin
will toggle ½ clock cycle HIGH and ½ clock cycle low. The user can use the PASS pin to count the number of
fails on the high speed link. In addition, there is a defined SER and DES register that will keep track of the
accumulated error count. The Serializer 903 GPO[0] pin will be assigned as a PASS flag error indicator for the
bidirectional control channel link.
Recovered
Pixel Clock
BISTEN
Case 1: No bit errors
Recovered
Pixel Data
PASS
Previous
³%,67´ 6WDWH
³%,67´ 6WDWH
Case 2: Bit error(s)
Recovered
Pixel Data
B
BB
B
PASS
Previous
³%,67´ 6WDWH
E
EE
E
Case 3: Bit error(s) AFTER BIST
Duration
Recovered
Pixel Data
PASS
Previous
³%,67´ 6WDWH
³%,67´ 6WDWH
B
³%,67´ 6WDWH
B = Bad Pixel
PE = Payload Error
BIST Duration
(when BISTEN=H)
Figure 33. BIST Timing Diagram
BIST Status
(when BISTEN=L)
Step 3: Stop at SPEED BIST by turning off BIST mode in the Deserializer to determine Pass/Fail.
To end BIST, the system must pull BISTEN pin of the Deserializer LOW. The BIST duration is fully defined by
the BISTEN width and Deserializer LOCK is HIGH; thus the Bit Error Rate is determined by how long the system
holds BISTEN HIGH.
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