DS90UB903QSQ Datasheet, PDF (24/45 Pages) Texas Instruments – DS90UB903Q/DS90UB904Q 10 - 43MHz 18 Bit Color FPD-Link III Serializer and Deserializer

DS90UB903Q, DS90UB904Q
SNLS332E – JUNE 2010 – REVISED APRIL 2013
www.ti.com
DESCRIPTION OF BIDIRECTIONAL CONTROL BUS AND I2C MODES
The I²C compatible interface allows programming of the DS90UB903Q, DS90UB904Q, or an external remote
device (such as a display) through the bidirectional control channel. Register programming transactions to/from
the DS90UB903Q/904Q chipset are employed through the clock (SCL) and data (SDA) lines. These two signals
have open-drain I/Os and both lines must be pulled-up to VDDIO by external resistor. Figure 4 shows the timing
relationships of the clock (SCL) and data (SDA) signals. Pull-up resistors or current sources are required on the
SCL and SDA busses to pull them high when they are not being driven low. A logic zero is transmitted by driving
the output low. A logic high is transmitted by releasing the output and allowing it to be pulled-up externally. The
appropriate pull-up resistor values will depend upon the total bus capacitance and operating speed. The
DS90UB903Q/904Q I²C bus data rate supports up to 100 kbps according to I²C specification.
To start any data transfer, the DS90UB903Q/904Q must be configured in the proper I²C mode. Each device can
function as an I²C slave proxy or master proxy depending on the mode determined by MODE pin. The Ser/Des
interface acts as a virtual bridge between Master Controller Unit (MCU) and the remote device. When the MODE
pin is set to High, the device is treated as a slave proxy; acts as a slave on behalf of the remote slave. When
addressing a remote peripheral or Serializer/Deserializer (not wired directly to the MCU), the slave proxy will
forward any byte transactions sent by the Master controller to the target device. When MODE pin is set to Low,
the device will function as a master proxy device; acts as a master on behalf of the I²C master controller. Note
that the devices must have complementary settings for the MODE configuration. For example, if the Serializer
MODE pin is set to High then the Deserializer MODE pin must be set to Low and vice-versa.
Bus Activity:
Master
SDA Line S
Slave
Address
7-bit Address 0
Register
Address
Data
P
Bus Activity:
Slave
A
A
A
C
C
C
K
K
K
Figure 25. Write Byte
Bus Activity:
Master
Slave
Address
Register
Address
Slave
Address
SDA Line S
7-bit Address 0
S
7-bit Address 1
Bus Activity:
Slave
A
A
A
C
C
C
K
K
K
Figure 26. Read Byte
Data
N
A
C
K
P
SDA
SCL
START
MSB
1
7-bit Slave Address
2
6
LSB
ACK
R/W
Direction
Bit
Acknowledge
from the Device
MSB
7
8
9
1
Data Byte
2
LSB N/ACK
*Acknowledge
or Not-ACK
8
9
Repeated for the Lower Data Byte
and Additional Data Transfers
STOP
Figure 27. Basic Operation
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