DS90UB903QSQ Datasheet, PDF (10/45 Pages) Texas Instruments – DS90UB903Q/DS90UB904Q 10 - 43MHz 18 Bit Color FPD-Link III Serializer and Deserializer

DS90UB903Q, DS90UB904Q
SNLS332E – JUNE 2010 – REVISED APRIL 2013
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Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
t_LHT
CML Low-to-High Transition
Time
R_L = 100Ω (Figure 6)
t_HLT
CML High-to-Low Transition
Time
R_L = 100Ω (Figure 6)
t_DIS
Data Input Setup to PCLK
2.0
Serializer Data Inputs (Figure 12)
t_DIH
Data Input Hold from PCLK
2.0
t_PLD
Serializer PLL Lock Time
R_L = 100Ω^{(1) (2)}
t_SD
Serializer Delay
R_T = 100Ω, PCLK = 10–43 MHz
Register 0x03h b[0] (TRFB = 1)
(Figure 14)
6.386T
+5
t_JIND
Serializer Output
Serializer output intrinsic deterministic
jitter . Measured (cycle-cycle) with
Deterministic Jitter
PRBS-7 test pattern
PCLK = 43 MHz⁽³⁾⁽⁴⁾
t_JINR
Serializer Output Random
Jitter
Serializer output intrinsic random jitter
(cycle-cycle). Alternating-1,0 pattern.
PCLK = 43 MHz⁽³⁾⁽⁴⁾
t_JINT
Serializer output peak-to-peak jitter
includes deterministic jitter, random
Peak-to-peak Serializer
jitter, and jitter transfer from serializer
Output Jitter
input. Measured (cycle-cycle) with
PRBS-7 test pattern.
PCLK = 43 MHz⁽³⁾⁽⁴⁾
λ_STXBW
Serializer Jitter Transfer
Function -3 dB Bandwidth
PCLK = 43 MHz, Default Registers
(Figure 20)⁽³⁾
δ_STX
Serializer Jitter Transfer
Function (Peaking)
PCLK = 43 MHz, Default Registers
(Figure 20)⁽³⁾
δ_STXf
Serializer Jitter Transfer
Function (Peaking
Frequency)
PCLK = 43 MHz, Default Registers
(Figure 20)⁽³⁾
Typ
150
150
1
6.386T
+ 12
0.13
0.04
0.396
1.90
0.944
500
Max
330
330
2
6.386T
+ 19.7
Units
ps
ps
ns
ns
ms
ns
UI
UI
UI
MHz
dB
kHz
(1) t_PLD and t_DDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK
(2) Specification is ensured by design.
(3) Typical values represent most likely parametric norms at 1.8V or 3.3V, T_A = +25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not ensured.
(4) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
t_RCP
Receiver Output Clock Period
t_RCP = t_TCP
t_PDC
PCLK Duty Cycle
Default Registers
SSCG[3:0] = OFF
PCLK
PCLK
23.3
45
t_CLH
LVCMOS Low-to-High Transition V_DDIO: 1.71V to 1.89V or
Time
3.0 to 3.6V,
1.3
t_CHL
LVCMOS High-to-Low Transition
C_L = 8 pF (lumped load) PCLK
Default Registers
Time
(Figure 16)⁽¹⁾
1.3
t_CLH
t_CHL
LVCMOS Low-to-High Transition
Time
LVCMOS High-to-Low Transition
Time
V_DDIO: 1.71V to 1.89V or
3.0 to 3.6V,
C_L = 8 pF (lumped load)
Default Registers
(Figure 16)⁽¹⁾
Deserializer ROUTn
Data Outputs
1.6
1.6
t_ROS
t_ROH
ROUT Setup Data to PCLK
ROUT Hold Data to PCLK
V_DDIO: 1.71V to 1.89V or
3.0V to 3.6V,
C_L = 8 pF (lumped load)
Default Registers
Deserializer ROUTn
Data Outputs
0.38T
0.38T
Typ
T
50
2.0
2.0
2.4
2.4
0.5T
0.5T
Max Units
100
ns
55
%
2.8
ns
2.8
3.3
ns
3.3
ns
(1) Specification is ensured by characterization and is not tested in production.
10
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