DS90UB903QSQ Datasheet, PDF (20/45 Pages) Texas Instruments – DS90UB903Q/DS90UB904Q 10 - 43MHz 18 Bit Color FPD-Link III Serializer and Deserializer

DS90UB903Q, DS90UB904Q
SNLS332E – JUNE 2010 – REVISED APRIL 2013
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Table 2. DS90UB904Q Control Registers (continued)
Addr
(Hex)
Name
Bits
Field
R/W
RESERVED
7:6 RESERVED
Auto Clock
5 AUTO_CLOCK
RW
OSS Select
4 OSS_SEL
RW
2
SSCG
3:0 SSCG
RESERVED
7:6 RESERVED
VDDIO Control
5 VDDIO CONTROL RW
VDDIO Mode
4 VDDIO MODE
RW
3
I²C Pass-Through
3
I²C PASS-
THROUGH
RW
Auto ACK
2 AUTO ACK
RW
RESERVED
1 RESERVED
RRFB
0 RRFB
RW
4
EQ Control
7:0 EQ
RW
5
RESERVED
7:0 RESERVED
Default
Description
00'b
0
0
0000'b
11'b
1
0
1
0
0
1
0x00'h
0x00'h
Reserved
1: Output PCLK or Internal 25 MHz Oscillator clock
0: Only PCLK when valid PCLK present
Output Sleep State Select
0: Outputs = TRI-STATE, when LOCK = L
1: Outputs = LOW , when LOCK = L
SSCG Select
0000: Normal Operation, SSCG OFF (default)
0001: fmod (kHz) PCLK/2168, fdev ±0.50%
0010: fmod (kHz) PCLK/2168, fdev ±1.00%
0011: fmod (kHz) PCLK/2168, fdev ±1.50%
0100: fmod (kHz) PCLK/2168, fdev ±2.00%
0101: fmod (kHz) PCLK/1300, fdev ±0.50%
0110: fmod (kHz) PCLK/1300, fdev ±1.00%
0111: fmod (kHz) PCLK/1300, fdev ±1.50%
1000: fmod (kHz) PCLK/1300, fdev ±2.00%
1001: fmod (kHz) PCLK/868, fdev ±0.50%
1010: fmod (kHz) PCLK/868, fdev ±1.00%
1011: fmod (kHz) PCLK/868, fdev ±1.50%
1100: fmod (kHz) PCLK/868, fdev ±2.00%
1101: fmod (kHz) PCLK/650, fdev ±0.50%
1110: fmod (kHz) PCLK/650, fdev ±1.00%
1111: fmod (kHz) PCLK/650, fdev ±1.50%
Reserved
Auto voltage control
0: Disable
1: Enable (auto detect mode)
VDDIO voltage set
Only used when VDDIOCONTROL = 0
0: 1.8V
1: 3.3V
I²C Pass-Through Mode
0: Disabled
1: Enabled
0: Disable
1: Enable
Reserved
Pixel Clock Edge Select
0: Parallel Interface Data is strobed on the Falling Clock
Edge
1: Parallel Interface Data is strobed on the Rising Clock
Edge.
EQ Gain
00'h = ~0.0 dB
01'h = ~4.5 dB
03'h = ~6.5 dB
07'h = ~7.5 dB
0F'h = ~8.0 dB
1F'h = ~11.0 dB
3F'h = ~12.5 dB
FF'h = ~14.0 dB
Reserved
20
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