AMC80 Datasheet, PDF (6/23 Pages) Texas Instruments – System Hardware Monitor with Two-Wire/SMBus Serial Interface

AMC80
SBOS559 – MAY 2011
TIMING DIAGRAM
SCL
SDA
t_(BUF)
P
S
t_(LOW)
t_R
t_F
t_(HDSTA)
t_(HIGH)
t_(HDDAT)
t_(SUSTA)
t_(SUDAT)
t_(HDSTA)
S
Figure 1. Serial Bus Interface Timing
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t_(SUSTO)
P
TIMING CHARACTERISTICS
At T_A –40°C to +125°C and V_S = 3V to 5.5V, unless otherwise noted.
FAST MODE
HIGH-SPEED MODE
PARAMETER
MIN
MAX
MIN
MAX UNITS
f_(SCL)
t_(BUF)
t_(HDSTA)
SCL operating frequency
Bus free time between STOP and START conditions
Hold time after repeated START condition. After this
period, the first clock is generated.
10
400
10
3400
kHz
600
160
ns
600
160
ns
t_(SUSTA)
t_(SUSTO)
t_(HDDAT)
t_(SUDAT)
t_(LOW)
t_(HIGH)
t_R
t_F
Repeated START condition setup time
STOP condition setup time
Data hold time
Data setup time
Clock low period
Clock high period
Clock/Data input rise time
Clock/Data input fall time
600
160
ns
600
160
ns
0 ⁽¹⁾
0 ⁽²⁾
ns
100
10
ns
1300
160
ns
600
60
ns
300
160
ns
300
160
ns
(1) For cases when the fall time of SCL is less than 20 ns and/or the rise time or fall time of SDA is less than 20 ns, the hold time should be
greater than 20 ns.
(2) For cases when the fall time of SCL is less than 10 ns and/or the rise or fall time of SDA is less than 10 ns, the hold time should be
greater than 10 ns.
6
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