AMC80 Datasheet, PDF (10/23 Pages) Texas Instruments – System Hardware Monitor with Two-Wire/SMBus Serial Interface

AMC80
SBOS559 – MAY 2011
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enable or disable the hardware interrupts. Additional digital inputs are provided for daisy-chaining the interrupt
output pin, INT. This configuration is achieved by connecting multiple external temperature sensors (for example,
the TMP75) to the board temperature interrupt (BTI) input and/or the GPI/CI input. The chassis intrusion (CI)
input is designed to accept an active high signal from an external circuit that latches (for example, when the
chassis from a server rack is removed).
INTERFACE AND CONTROL
The SMBus control lines in the AMC80 include SDA, SCL, and the A0 to A2 address pins, which allow up to
eight AMC80 devices to be on the same bus. The AMC80 can only operate as a slave device. The SCL line
controls only the serial interface; all other clock-related functions within the AMC80 (such as the ADC and fan
counters) operate with a separate asynchronous internal clock. The default power-on SMBus address for the
AMC80 is '0101'(A2)(A1)(A0) binary, where (A2)(A1)(A0) is the SMBus address.
When using the SMBus interface, a write command always consists of the AMC80 SMBus interface address
byte, followed by the internal address register byte, and then the data byte (see Figure 8).
See Figure 9 for the read operation timing. There are two cases for a read operation:
1. If the contents of the Internal Address Register are known, simply read the AMC80 with the SMBus interface
address byte, followed by the data byte read from the ADC80.
2. If the internal Address Register contents are unknown, write to the AMC80 with the SMBus interface address
byte, followed by the internal address register bye. Then restart the serial communication with a read that
consist of the SMBus interface address byte, followed by the data byte read from the AMC80.
REGISTER
Configuration Register
Interrupt Status Register 1
Interrupt Status Register 2
Interrupt Mask Register 1
Interrupt Mask Register 2
Fan Divisor/RST_OUT/OS Register
OS Configuration/Temperature Resolution
Register
Conversion Rate Register
Voltage/Temperature Channel Disable
Register
Input Mode Register
ADC Control Register
Conversion Rate Count Register
Value RAM Register
Value RAM Register
Value RAM Register
Value RAM Register
Table 1. Register Overview
INTERNAL
ADDRESS
(HEX)
00
01
02
03
04
05
POWER-ON
VALUE
(HEX)
08
xx
xx
00
00
14
Indeterminate
Indeterminate
NOTES
FAN1 and FAN2 divisor = 2 (count of 153 = 4400 RPM)
06
x1
Four MSBs are indeterminate
07
40
08
00
Allows voltage monitoring inputs to be disabled
09
0A
0B
20 to 29
2A to 3D
3E
3F
00
02
40
xx
Indeterminate
xx
Indeterminate
80
09
10
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