AMC80 Datasheet, PDF (17/23 Pages) Texas Instruments – System Hardware Monitor with Two-Wire/SMBus Serial Interface

AMC80
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INTERRUPT MASK REGISTERS
SBOS559 – MAY 2011
Table 6. Interrupt Mask Register 1 (Address = 03h, Default = 00h)
BIT
NAME
0
CH0
1
CH1
2
CH2
3
CH3
4
CH4
5
CH5
6
CH6
7
INT_IN
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DESCRIPTION
'1' disables the corresponding interrupt status bit in Table 4 to trigger the INT interrupt.
Table 7. Interrupt Mask Register 2 (Address = 04h, Default = 00h)
BIT
NAME
0
Hot Temperature
1
BTI
2
FAN 1
3
FAN 2
4
GPI/CI
5
OS
6
INT Interrupt Mode
Select
7
OS Interrupt Mode
Select
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
DESCRIPTION
'1' disables the corresponding interrupt status bit in Table 5 to trigger the INT interrupt.
R/W '0' selects Default Interrupt mode. '1' selects One-Time Interrupt mode.
R/W '0' selects Comparator mode. '1' selects One-Time Interrupt mode.
FAN DIVISOR/RST_OUT/OS REGISTER
Table 8. Fan Divisor/RST_OUT/OS Register (Address = 05h, Default = 14h)
BIT
NAME
TYPE
DESCRIPTION
0
FAN1 Mode Select
R/W '1' selects the level-sensitive input mode. '0' selects the fan count mode for the FAN1 input.
1
FAN2 Mode Select
R/W '1' selects the level-sensitive input mode. '0' selects the fan count mode for the FAN2 input.
2
FAN1 RPM Control 1 R/W FAN1 speed control:
'00' = divide by 1.
'01' = divide by 2.
'10' = divide by 4.
3
FAN1 RPM Control 0 R/W _{'11' = divide by 8.}
If level-sensitive input is selected, '01' selects an active-low input and '00' selects an
active-high input.
4
FAN2 RPM Control 1 R/W FAN2 speed control:
'00' = divide by 1.
'01' = divide by 2.
'10' = divide by 4.
5
FAN2 RPM Control 0 R/W _{'11' = divide by 8.}
If level select input is selected, '01' selects an active-low input and '00' selects an active-high
input.
6
OS Pin Enable
R/W
'1' enables OS mode on the RST_OUT/OS pin when bit 7 is set to '0'.
NOTE: When bits 6 and 7 are both set to '1', the RST_OUT/OS pin is disabled.
7
RST_OUT Pin Enable
R/W
'1' enables RST_OUT mode on the RST_OUT/OS pin when bit 6 is set to '0'.
NOTE: When bits 6 and 7 are both set to '1', the RST_OUT/OS pin is disabled.
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