MSP430BT5190_15 Datasheet, PDF (56/105 Pages) Texas Instruments – Mixed-Signal Microcontroller

MSP430BT5190
SLAS703B – APRIL 2010 – REVISED AUGUST 2015
www.ti.com
UCS control 8
Table 6-18. UCS Registers (Base Address: 0160h) (continued)
REGISTER DESCRIPTION
REGISTER
UCSCTL8
10h
OFFSET
Table 6-19. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
System control
Bootstrap loader configuration area
JTAG mailbox control
JTAG mailbox input 0
JTAG mailbox input 1
JTAG mailbox output 0
JTAG mailbox output 1
Bus Error vector generator
User NMI vector generator
System NMI vector generator
Reset vector generator
REGISTER
SYSCTL
SYSBSLC
SYSJMBC
SYSJMBI0
SYSJMBI1
SYSJMBO0
SYSJMBO1
SYSBERRIV
SYSUNIV
SYSSNIV
SYSRSTIV
OFFSET
00h
02h
06h
08h
0Ah
0Ch
0Eh
18h
1Ah
1Ch
1Eh
Table 6-20. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
Shared reference control
REGISTER
REFCTL
00h
OFFSET
Table 6-21. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
Port P1 input
Port P1 output
Port P1 direction
Port P1 pullup/pulldown enable
Port P1 drive strength
Port P1 selection
Port P1 interrupt vector word
Port P1 interrupt edge select
Port P1 interrupt enable
Port P1 interrupt flag
Port P2 input
Port P2 output
Port P2 direction
Port P2 pullup/pulldown enable
Port P2 drive strength
Port P2 selection
Port P2 interrupt vector word
Port P2 interrupt edge select
Port P2 interrupt enable
Port P2 interrupt flag
REGISTER
P1IN
P1OUT
P1DIR
P1REN
P1DS
P1SEL
P1IV
P1IES
P1IE
P1IFG
P2IN
P2OUT
P2DIR
P2REN
P2DS
P2SEL
P2IV
P2IES
P2IE
P2IFG
OFFSET
00h
02h
04h
06h
08h
0Ah
0Eh
18h
1Ah
1Ch
01h
03h
05h
07h
09h
0Bh
1Eh
19h
1Bh
1Dh
56
Detailed Description
Copyright © 2010–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430BT5190