MSP430BT5190_15 Datasheet, PDF (13/105 Pages) Texas Instruments – Mixed-Signal Microcontroller

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MSP430BT5190
SLAS703B – APRIL 2010 – REVISED AUGUST 2015
5 Specifications
5.1 Absolute Maximum Ratings⁽¹⁾
over operating free-air temperature range (unless otherwise noted)
MIN
MAX UNIT
Voltage applied at V_CC to V_SS
Voltage applied to any pin (excluding VCORE)⁽²⁾
Diode current at any device pin
Storage temperature range, T_stg ⁽³⁾
Maximum junction temperature, T_J
–0.3
4.1
V
–0.3 V_CC + 0.3
V
±2 mA
–55
105
°C
95
°C
(1) Stresses beyond those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to V_SS. VCORE is for internal device use only. No external DC loading or voltage should be applied.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2 ESD Ratings
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾
V_(ESD) Electrostatic discharge _{Charged-device model (CDM), per JEDEC specification JESD22-C101(2)}
VALUE
±1000
±250
UNIT
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
5.3 Recommended Operating Conditions
Typical values are specified at V_CC = 3.3 V and T_A = 25°C (unless otherwise noted)
MIN NOM MAX UNIT
V_CC
V_SS
T_A
T_J
C_VCORE
C_DVCC/C_V
CORE
f_SYSTEM
Supply voltage during program execution and flash programming
(AV_CC = DV_CC1/2/3/4 = DV_CC) ^{(1) (2)}
Supply voltage (AV_SS = DV_SS1/2/3/4 = DV_SS)
Operating free-air temperature
Operating junction temperature
Recommended capacitor at VCORE⁽³⁾
I version
I version
Capacitor ratio of DVCC to VCORE
Processor frequency (maximum MCLK
frequency)^{(4) (5)} (see Figure 5-1)
PMMCOREVx = 0, 1.8 V ≤ V_CC ≤ 3.6 V
PMMCOREVx = 1, 2.0 V ≤ V_CC ≤ 3.6 V
PMMCOREVx = 2, 2.2 V ≤ V_CC ≤ 3.6 V
PMMCOREVx = 3, 2.4 V ≤ V_CC ≤ 3.6 V
1.8
3.6 V
0
–40
–40
470
V
85 °C
85 °C
nF
10
0
8.0
0
12.0
MHz
0
20.0
0
25.0
(1) TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
(2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the Section 5.23 threshold parameters for
the exact values and further details.
(3) A capacitor tolerance of ±20% or better is required.
(4) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the
specified maximum frequency.
(5) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
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Specifications
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