TMS320DM365_16 Datasheet, PDF (55/210 Pages) Texas Instruments – Digital Media System-on-Chip (DMSoC)

TMS320DM365
www.ti.com
SPRS457E – MARCH 2009 – REVISED JUNE 2011
Figure 3-2. Clocking Architecture
Oscillator (MXI1/MXO1)
19.2/24/27/36 Mhz
PLLC1
PLLC2
SPI4
UART0
CLKOUT0
CLKOUT2
DIV1
MMC/SD0
McBSP
MMC/SD1
AEMIF
UART1
SPI0-3
GPIO
AINTC
PHYCLKSRC
HDVICP ARMSS
USB PHY
MJCP
VPSS
USB
VENC_CLK_SRC
EXTCLK
PCLK
VPSS_MUXSEL
VPBE
VPFE
DIV2
I2C
PWM0-3
TIMER0-3/
WDT
RTO
ADC
CLKOUT1
Voice
Codec
EMAC
HPI
EDMA
DDR
PHY
DDRCLKS
VCLK
DDR2
EMIF
DIV3
KEYSCLKS
PRTCCLKS
KeyScan
PRTCSS
32 Khz
Oscillator
3.3.2 PLL Controller Module
Two PLL controllers provide clocks to different components of the chip. The PLL controller 1 (PLLC1)
provides clocks to most of the components of the chip. The PLL controller 2 (PLLC2) provides clocks to
the DDR PHY and is also capable of providing clocks to the ARM, USB, VPSS or the Voice Codec
modules instead as well.
As a module, the PLL controller provides the following:
• Glitch-free transitions (on changing PLL settings)
• Domain clocks alignment
• Clock gating
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Device Configurations
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