TMS320DM365_16 Datasheet, PDF (159/210 Pages) Texas Instruments – Digital Media System-on-Chip (DMSoC)

TMS320DM365
www.ti.com
SPRS457E – MARCH 2009 – REVISED JUNE 2011
6.15 Serial Port Interface (SPI)
The SPI module provides a programmable length shift register which allows serial communication with
other SPI devices through a 3 or 4 wire interface (Clock, Data In, Data Out, and Chip-select). The SPI
supports the following features:
• Master and Slave mode operation is supported on all SPI ports (master mode means that the device
provides the serial clock)
• 2 chip selects for interfacing to multiple slave SPI devices.
• 3 or 4 wire interface (Clock, Data In, Data Out, and Enable)
• Unique interrupt for each SPI port (except SPI4)
• Separate EDMA events for SPI Receive and Transmit for each SPI port (except SPI4)
• 16-bit shift register
• Receive buffer register
• Programmable character length (2 to 16 bits)
• Programmable SPI clock frequency range
• 8-bit clock prescaler
• Programmable clock phase (delay or no delay)
• Programmable clock polarity
Note: SPI4 slave mode does not support Chip-select input, only supports 3-wire interface.
The SPI modules do not support the following features:
• GPIO mode. GPIO functionality is supported by the GIO modules for those SPI pins that are
multiplexed with GPIO signals.
6.15.1 SPI Peripheral Register Description(s)
Table 6-61 lists the SPI registers, their corresponding acronyms, and the device memory locations
(offsets). These offsets apply to all device SPI modules.
OFFSET
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h - 38h
3Ch
40h
44h
48h
4Ch
50h-5Ch
60h
64h
Table 6-61. SPI Registers
ACRONYM
SPIGCR0
SPIGCR1
SPIINT
SPILVL
SPIFLG
SPIPC0
-
SPIPC2
-
SPIDAT1
SPIBUF
SPIEMU
SPIDELAY
SPIDEF
SPIFMT0
INTVECT0
INTVECT1
REGISTER DESCRIPTION
SPI global control register 0
SPI global control register 1
SPI interrupt register
SPI interrupt level register
SPI flag register
SPI pin control register
Reserved
SPI pin control register 2
Reserved
SPI shift register
SPI buffer register
SPI emulation register
SPI delay register
SPI default chip select register
SPI data format register 0
SPI interrupt vector register 0
SPI interrupt vector register 1
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Peripheral Information and Electrical Specifications 159
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