TMS320DM365_16 Datasheet, PDF (1/210 Pages) Texas Instruments – Digital Media System-on-Chip (DMSoC)

TMS320DM365
www.ti.com
SPRS457E – MARCH 2009 – REVISED JUNE 2011
TMS320DM365
Digital Media System-on-Chip (DMSoC)
Check for Samples: TMS320DM365
1 TMS320DM365 Digital Media System-on-Chip (DMSoC)
1.1 Features
12
• Highlights
– High-Performance Digital Media
System-on-Chip (DMSoC)
– Up to 300-MHz ARM926EJ-S Clock Rate
– Two Video Image Co-processors
(HDVICP, MJCP) Engines
– Supports a Range of Encode, Decode, and
Video Quality Operations
– Video Processing Subsystem
• HW Face Detect Engine
• Resize Engine from 1/16x to 8x
• 16-Bit Parallel AFE (Analog Front-End)
Interface Up to 120 MHz
• 4:2:2 (8-/16-bit) Interface
• 8-/16-bit YCC and Up to 24-Bit RGB888
Digital Output
• 3 DACs for HD Analog Video Output
• Hardware On-Screen Display (OSD)
– Capable of 720p 30fps H.264 video
processing
Note: 216-MHz is only capable of D1
processing
– Peripherals include EMAC, USB 2.0 OTG,
DDR2/NAND, 5 SPIs, 2 UARTs, 2
MMC/SD/SDIO, Key Scan
– 8 Different Boot Modes and Configurable
Power-Saving Modes
– Pin-to-pin and software compatible with
DM368
– Extended temperature (-40ºC – 85ºC)
available for 300-MHz device
– 3.3-V and 1.8-V I/O, 1.2-V/1.35-V Core
– 338-Pin Ball Grid Array at 65nm Process
Technology
• High-Performance Digital Media
System-on-Chip (DMSoC)
– 216-, 270-, 300-MHz ARM926EJ-S Clock Rate
– Fully Software-Compatible With ARM9™
– Extended temperature available for 300-MHz
device
• ARM926EJ-S™ Core
– Support for 32-Bit and 16-Bit
(Thumb® Mode) Instruction Sets
– DSP Instruction Extensions and Single Cycle
MAC
– ARM® Jazelle® Technology
– Embedded ICE-RT Logic for Real-Time
Debug
• ARM9 Memory Architecture
– 16K-Byte Instruction Cache
– 8K-Byte Data Cache
– 32K-Byte RAM
– 16K-Byte ROM
– Little Endian
• Two Video Image Co-processors
(HDVICP, MJCP) Engines
– Support a Range of Encode and Decode
Operations, up to D1 on 216-MHz device and
up to 720p on the 270- and 300-MHz parts
– H.264, MPEG4, MPEG2, MJPEG, JPEG,
WMV9/VC1
• Video Processing Subsystem
– Front End Provides:
• HW Face Detect Engine
• Hardware IPIPE for Real-Time Image
Processing
– Resize Engine
– Resize Images From 1/16x to 8x
– Separate Horizontal/Vertical
Control
– Two Simultaneous Output Paths
• IPIPE Interface (IPIPEIF)
• Image Sensor Interface (ISIF) and CMOS
Imager Interface
• 16-Bit Parallel AFE (Analog Front End)
Interface Up to 120 MHz
• Glueless Interface to Common Video
Decoders
• BT.601/BT.656/BT.1120 Digital YCbCr
4:2:2 (8-/16-Bit) Interface
• Histogram Module
• Lens distortion correction module (LDC)
1
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2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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