TMS320DM365_16 Datasheet, PDF (163/210 Pages) Texas Instruments – Digital Media System-on-Chip (DMSoC)

TMS320DM365
www.ti.com
SPRS457E – MARCH 2009 – REVISED JUNE 2011
Table 6-65. General Input Timing Requirements in Slave Mode⁽¹⁾
NO.
9
10
11
t_c(CLK)
t_w(CLKH)
t_w(CLKL)
15
t_su(SIMO-CLK)
16
t_h(CLK-SIMO)
Cycle time, SPI_SCLK
Pulse width, SPI_SCLK high
Pulse width, SPI_SCLK low
Setup time, SPI_SIMO data valid before receive falling edge of
SPI_SCLK, 3-/4-pin mode,
polarity = 0, phase = 0
Setup time, SPI_SIMO data valid before receive rising edge of
SPI_SCLK, 3-/4-pin mode,
polarity = 0, phase = 1
Setup time, SPI_SIMO data valid before receive rising edge of
SPI_SCLK, 3-/4-pin mode,
polarity = 1, phase = 0
Setup time, SPI_SIMO data valid before receive falling edge of
SPI_SCLK, 3-/4-pin mode,
polarity = 1, phase = 1
Hold time, SPI_SIMO data valid after receive falling edge of
SPI_SCLK, 3-/4-pin mode,
polarity = 0, phase = 0
Hold time, SPI_SIMO data valid after receive rising edge of
SPI_SCLK, 3-/4-pin mode,
polarity = 0, phase = 1
Hold time, SPI_SIMO data valid after receive rising edge of
SPI_SCLK, 3-/4-pin mode,
polarity = 1, phase = 0
Hold time, SPI_SIMO data valid after receive falling edge of
SPI_SCLK, 3-/4-pin mode,
polarity = 1, phase = 1
MIN
greater of 2P
or 25
.5(t_c(CLK)) -
1.25
.5(t_c(CLK)) -
1.25
4
4
4
4
4
4
4
4
MAX UNIT
256P ns
ns
ns
ns
ns
(1) T = period of SPI_SCLK; For SPI0, SPI1, SPI2, and SPI3, P = period of SPI core clock (PLL1SYSCLK4). For SPI4, P = period of SPI
core clock (OSCIN).
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Peripheral Information and Electrical Specifications 163
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