TMS320DM365_16 Datasheet, PDF (131/210 Pages) Texas Instruments – Digital Media System-on-Chip (DMSoC)

TMS320DM365
www.ti.com
SPRS457E – MARCH 2009 – REVISED JUNE 2011
• Programmable Horizontal Sampling Points in a window
• Programmable Vertical Sampling Points in a window
The Hardware 3A (H3A) register memory mapping (offsets) is shown in Table 6-43.
Offset
0h
4h
8h
Ch
10h
18h
4Ch
50h
54h
58h
5Ch
60h
64h
68h
6Ch
70h
74h
78h
Table 6-43. Hardware 3A Statistics Generation (AE, AF, AWB) (H3A) Registers
Acronym
PID
PCR
AFPAX1
AFPAX2
AFPAXSTART
AFBUFST
AEWWIN1
AEWINSTART
AEWINBLK
AEWSUBWIN
AEWBUFST
RSDR_ADDR
LINE_START
VFV_CFG1
VFV_CFG2
VFV_CFG3
VFV_CFG4
HFV_THR
Register Description
Peripheral Revision and Class Information
Peripheral Control Register
Setup for the AF Engine Paxel Configuration
Setup for the AF Engine Paxel Configuration
Start Position for AF Engine Paxels
SDRAM/DDRAM Start address for AF Engine
Configuration for AE/AWB Windows
Start position for AE/AWB Windows
Start position and height for black line of AE/AWB Windows
Configuration for subsample data in AE/AWB window
SDRAM/DDRAM Start address for AE/AWB Engine Output Data
AE/AWB Engine Configuration
Line start position for ISIF interface
AF Vertical Focus Configuration 1 Register
AF Vertical Focus Configuration 2 Register
AF Vertical Focus Configuration 3 Register
AF Vertical Focus Configuration 4 Register
Configures the Horizontal Thresholds for the AF IIR filters
6.12.1.5 Face Detection Module
The following features are supported on the Face Detection module:
• High detection rate of close to 100% under most conditions
• Allows detection in different directions - up, left, and right
• Allows detection with rotation in plane (RIP) - ±45°, @ 0°/+90°/-90°
• Allows detection for rotation out of plane (ROP)
– Horizontal (left/right) pan: ±60°
– Vertical (up/down) tilt: ±30°
• Configurable minimum face size of 20 - 40 pixels
• Configurable region of interest in the input frame
• Configurable start position in the input frame
• Supports up to 35 face detections in a single frame
• Interrupt generation to ARM using the Video Processing Subsystem (VPSS) multiplexed interrupt
mechanism
• Robust performance in low light conditions, night vision, monochromatic, and false color sensing as
skin tone not used for face detection
• Supported input size is (256X192)
• Input format is 8-bit gray scale data
The Face Detection Module register memory mapping (offsets) is shown in Table 6-44.
Copyright © 2009–2011, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 131
Submit Documentation Feedback
Product Folder Link(s): TMS320DM365