BQ28Z560-R1 Datasheet, PDF (52/60 Pages) Texas Instruments – Single Cell Li-Ion Battery Gas Gauge and Protection

bq28z560-R1
SLUSBD3 – APRIL 2013
Incremental read at the maximum allowed read address:
S ADDR[6:0] 0 A CMD[7:0]
A Sr ADDR[6:0] 1 A DATA[7:0]
www.ti.com
A . . . DATA[7:0] N P
Address
0x7F
Data From
addr 0x7F
Data From
addr 0x00
The I²C engine releases both SDA and SCL if the I²C bus is held low for t_(BUSERR). If the gas gauge was holding
the lines, releasing them frees the master to drive the lines. If an external condition is holding either of the lines
low, the I²C engine enters the low-power SLEEP mode.
I²C Timeout
The I²C engine will release both SDA and SCL if the I²C bus is held low for about 2 s. If the bq28z560-R1 was
holding the lines, releasing them will free the master to drive the lines.
I²C Command Waiting Time
To ensure getting the correct results of a command with the 400 KHz I²C operation, a proper waiting time should
be added between issuing the command and reading results. For subcommands, the following diagram shows
the waiting time required between issuing the control command and reading the status with the exception of the
checksum command. A 100-ms waiting time is required between the checksum command and reading result. For
read-write standard commands, a minimum of 2 s is required to get the result updated. For read-only standard
commands, there is no waiting time required, but the host should not issue all standard commands more than
two times per second. Otherwise, the gauge could result in a reset issue due to the expiration of the watchdog
timer.
S ADDR[6:0] 0 A
S ADDR[6:0] 0 A
CMD[7:0]
CMD[7:0]
A DATA [7:0] A DATA [7:0] A P 66ms
A Sr ADDR[6:0] 1 A DATA [7:0] A DATA [7:0]
Waiting time between control subcommand and reading results
N P 66ms
S ADDR[6:0] 0 A CMD[7:0] A Sr ADDR[6:0] 1 A DATA [7:0] A DATA [7:0] A
DATA [7:0] A DATA [7:0] N P 66ms
Waiting time between continuous reading results
The I²C clock stretch could happen in a typical application. A maximum 80-ms clock stretch could be observed
during the flash updates. There can be up to a 270-ms clock stretch after the OCV command is issued.
52
Submit Documentation Feedback
Product Folder Links: bq28z560-R1
Copyright © 2013, Texas Instruments Incorporated